401 lines
24 KiB
Diff
401 lines
24 KiB
Diff
diff --git a/projects/pluto/system_bd.tcl b/projects/pluto/system_bd.tcl
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index 8a9634b9..85c1bc28 100644
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--- a/projects/pluto/system_bd.tcl
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+++ b/projects/pluto/system_bd.tcl
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@@ -47,6 +47,12 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 17
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+ad_ip_parameter sys_ps7 CONFIG.PCW_EN_ENET0 1
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+ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_PERIPHERAL_ENABLE 1
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+ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}
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+ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1
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+ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53}
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+
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ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 0
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ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 0
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ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1
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@@ -54,16 +60,28 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}
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ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 0
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ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE 1
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-ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 0
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ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO
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+
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+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 1
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+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_SD0_IO "MIO 40 .. 45"
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+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_ENABLE 1
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+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_IO "MIO 47"
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+ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_47_PULLUP {enabled}
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+ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_47_SLEW {slow}
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+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_POW_ENABLE 0
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+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_WP_ENABLE 0
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+
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ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0
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ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_IO MIO
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-ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO {MIO 52}
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+ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO {MIO 46}
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ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1
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+ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_46_SLEW {slow}
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+ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_46_PULLUP {enabled}
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+
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ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE
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ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_0_PULLUP {enabled}
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diff --git a/projects/pluto/system_constr.xdc b/projects/pluto/system_constr.xdc
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index 67a9558c..9bf4e924 100644
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--- a/projects/pluto/system_constr.xdc
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+++ b/projects/pluto/system_constr.xdc
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@@ -1,69 +1,69 @@
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# constraints
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# ad9361 (SWAP == 0x1)
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-set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 } [get_ports rx_clk_in]
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-set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx_frame_in]
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-set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
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-set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
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-set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
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-set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
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-set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
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-set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
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-set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
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-set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
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-set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
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-set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
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-set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
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-set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
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-
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-set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS18} [get_ports tx_clk_out]
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-set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18} [get_ports tx_frame_out]
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-set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
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-set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
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-set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
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-set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
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-set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
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-set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
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-set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
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-set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
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-set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
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-set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
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-set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
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-set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
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-
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-set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]
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-set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]
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-set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]
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-set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]
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-set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]
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-set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]
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-set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]
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-set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]
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-
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-set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]
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-set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]
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-set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]
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-set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]
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-
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-set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]
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-set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS18} [get_ports gpio_resetb]
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-
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-set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports enable]
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-set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports txnrx]
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-
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-set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl]
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-set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda]
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-
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-set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn]
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-set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports spi_clk]
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-set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports spi_mosi]
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-set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports spi_miso]
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-
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-set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS18} [get_ports pl_spi_clk_o]
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-set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18} [get_ports pl_spi_miso]
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-set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports pl_spi_mosi]
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-
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-set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS18} [get_ports clk_out]
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+set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS18 } [get_ports rx_clk_in]
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+set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS18 } [get_ports rx_frame_in]
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+set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
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+set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
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+set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
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+set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
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+set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
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+set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
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+set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
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+set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
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+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
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+set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
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+set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
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+set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
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+
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+set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18} [get_ports tx_clk_out]
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+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS18} [get_ports tx_frame_out]
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+set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
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+set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
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+set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
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+set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
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+set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
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+set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
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+set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
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+set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
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+set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
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+set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
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+set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
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+set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
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+
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+set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]
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+set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]
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+set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]
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+set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]
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+set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]
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+set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]
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+set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]
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+set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]
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+
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+set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]
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+set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]
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+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]
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+set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]
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+
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+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]
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+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS18} [get_ports gpio_resetb]
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+
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+set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS18} [get_ports enable]
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+set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS18} [get_ports txnrx]
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+
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+set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl]
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+set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda]
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+
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+set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn]
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+set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS18} [get_ports spi_clk]
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+set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports spi_mosi]
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+set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports spi_miso]
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+
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+set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS18} [get_ports pl_spi_clk_o]
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+set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS18} [get_ports pl_spi_miso]
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+set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS18} [get_ports pl_spi_mosi]
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+
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+set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS18} [get_ports clk_out]
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create_clock -name rx_clk -period 16.27 [get_ports rx_clk_in]
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@@ -80,123 +80,123 @@ set_input_jitter clk_fpga_1 0.15
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set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*]
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set_property SLEW SLOW [get_ports *fixed_io_mio*]
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set_property DRIVE 8 [get_ports *fixed_io_mio*]
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-set_property -dict {PACKAGE_PIN D8 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]]
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-set_property -dict {PACKAGE_PIN A5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]]
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-set_property -dict {PACKAGE_PIN A8 } [get_ports fixed_io_mio[ 2]]
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-set_property -dict {PACKAGE_PIN A7 } [get_ports fixed_io_mio[ 3]]
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-set_property -dict {PACKAGE_PIN C8 } [get_ports fixed_io_mio[ 4]]
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-set_property -dict {PACKAGE_PIN A9 } [get_ports fixed_io_mio[ 5]]
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-set_property -dict {PACKAGE_PIN A10 } [get_ports fixed_io_mio[ 6]]
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-set_property -dict {PACKAGE_PIN D9 } [get_ports fixed_io_mio[ 7]]
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-set_property -dict {PACKAGE_PIN B6 } [get_ports fixed_io_mio[ 8]]
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+set_property -dict {PACKAGE_PIN E6 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]]
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+set_property -dict {PACKAGE_PIN A7 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]]
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+set_property -dict {PACKAGE_PIN B8 } [get_ports fixed_io_mio[ 2]]
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+set_property -dict {PACKAGE_PIN D6 } [get_ports fixed_io_mio[ 3]]
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+set_property -dict {PACKAGE_PIN B7 } [get_ports fixed_io_mio[ 4]]
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+set_property -dict {PACKAGE_PIN A6 } [get_ports fixed_io_mio[ 5]]
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+set_property -dict {PACKAGE_PIN A5 } [get_ports fixed_io_mio[ 6]]
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+set_property -dict {PACKAGE_PIN D8 } [get_ports fixed_io_mio[ 7]]
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+set_property -dict {PACKAGE_PIN D5 } [get_ports fixed_io_mio[ 8]]
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set_property -dict {PACKAGE_PIN B5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]]
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-set_property -dict {PACKAGE_PIN D6 PULLTYPE PULLUP} [get_ports fixed_io_mio[10]]
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-set_property -dict {PACKAGE_PIN B10 PULLTYPE PULLUP} [get_ports fixed_io_mio[11]]
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-set_property -dict {PACKAGE_PIN B7 PULLTYPE PULLUP} [get_ports fixed_io_mio[12]]
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-set_property -dict {PACKAGE_PIN C6 PULLTYPE PULLUP} [get_ports fixed_io_mio[13]]
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-set_property -dict {PACKAGE_PIN B9 PULLTYPE PULLUP} [get_ports fixed_io_mio[14]]
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-set_property -dict {PACKAGE_PIN D10 PULLTYPE PULLUP} [get_ports fixed_io_mio[15]]
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-set_property -dict {PACKAGE_PIN A15 PULLTYPE PULLUP} [get_ports fixed_io_mio[16]]
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-set_property -dict {PACKAGE_PIN D11 PULLTYPE PULLUP} [get_ports fixed_io_mio[17]]
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-set_property -dict {PACKAGE_PIN B15 PULLTYPE PULLUP} [get_ports fixed_io_mio[18]]
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-set_property -dict {PACKAGE_PIN C12 PULLTYPE PULLUP} [get_ports fixed_io_mio[19]]
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-set_property -dict {PACKAGE_PIN E15 PULLTYPE PULLUP} [get_ports fixed_io_mio[20]]
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-set_property -dict {PACKAGE_PIN C11 PULLTYPE PULLUP} [get_ports fixed_io_mio[21]]
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-set_property -dict {PACKAGE_PIN D15 PULLTYPE PULLUP} [get_ports fixed_io_mio[22]]
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-set_property -dict {PACKAGE_PIN A14 PULLTYPE PULLUP} [get_ports fixed_io_mio[23]]
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-set_property -dict {PACKAGE_PIN B14 PULLTYPE PULLUP} [get_ports fixed_io_mio[24]]
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-set_property -dict {PACKAGE_PIN C14 PULLTYPE PULLUP} [get_ports fixed_io_mio[25]]
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-set_property -dict {PACKAGE_PIN A13 PULLTYPE PULLUP} [get_ports fixed_io_mio[26]]
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-set_property -dict {PACKAGE_PIN D14 PULLTYPE PULLUP} [get_ports fixed_io_mio[27]]
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+set_property -dict {PACKAGE_PIN E9 PULLTYPE PULLUP} [get_ports fixed_io_mio[10]]
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+set_property -dict {PACKAGE_PIN C6 PULLTYPE PULLUP} [get_ports fixed_io_mio[11]]
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+set_property -dict {PACKAGE_PIN D9 PULLTYPE PULLUP} [get_ports fixed_io_mio[12]]
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+set_property -dict {PACKAGE_PIN E8 PULLTYPE PULLUP} [get_ports fixed_io_mio[13]]
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+set_property -dict {PACKAGE_PIN C5 PULLTYPE PULLUP} [get_ports fixed_io_mio[14]]
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+set_property -dict {PACKAGE_PIN C8 PULLTYPE PULLUP} [get_ports fixed_io_mio[15]]
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+set_property -dict {PACKAGE_PIN C16 PULLTYPE PULLUP} [get_ports fixed_io_mio[16]]
|
|
+set_property -dict {PACKAGE_PIN C13 PULLTYPE PULLUP} [get_ports fixed_io_mio[17]]
|
|
+set_property -dict {PACKAGE_PIN C15 PULLTYPE PULLUP} [get_ports fixed_io_mio[18]]
|
|
+set_property -dict {PACKAGE_PIN E16 PULLTYPE PULLUP} [get_ports fixed_io_mio[19]]
|
|
+set_property -dict {PACKAGE_PIN A14 PULLTYPE PULLUP} [get_ports fixed_io_mio[20]]
|
|
+set_property -dict {PACKAGE_PIN D15 PULLTYPE PULLUP} [get_ports fixed_io_mio[21]]
|
|
+set_property -dict {PACKAGE_PIN A12 PULLTYPE PULLUP} [get_ports fixed_io_mio[22]]
|
|
+set_property -dict {PACKAGE_PIN F12 PULLTYPE PULLUP} [get_ports fixed_io_mio[23]]
|
|
+set_property -dict {PACKAGE_PIN A11 PULLTYPE PULLUP} [get_ports fixed_io_mio[24]]
|
|
+set_property -dict {PACKAGE_PIN A10 PULLTYPE PULLUP} [get_ports fixed_io_mio[25]]
|
|
+set_property -dict {PACKAGE_PIN E13 PULLTYPE PULLUP} [get_ports fixed_io_mio[26]]
|
|
+set_property -dict {PACKAGE_PIN C18 PULLTYPE PULLUP} [get_ports fixed_io_mio[27]]
|
|
set_property -dict {PACKAGE_PIN B12 PULLTYPE PULLUP} [get_ports fixed_io_mio[28]]
|
|
-set_property -dict {PACKAGE_PIN D13 PULLTYPE PULLUP} [get_ports fixed_io_mio[29]]
|
|
-set_property -dict {PACKAGE_PIN A12 PULLTYPE PULLUP} [get_ports fixed_io_mio[30]]
|
|
-set_property -dict {PACKAGE_PIN C13 PULLTYPE PULLUP} [get_ports fixed_io_mio[31]]
|
|
+set_property -dict {PACKAGE_PIN C12 PULLTYPE PULLUP} [get_ports fixed_io_mio[29]]
|
|
+set_property -dict {PACKAGE_PIN C10 PULLTYPE PULLUP} [get_ports fixed_io_mio[30]]
|
|
+set_property -dict {PACKAGE_PIN C11 PULLTYPE PULLUP} [get_ports fixed_io_mio[31]]
|
|
|
|
set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*]
|
|
set_property SLEW SLOW [get_ports *fixed_io_ps*]
|
|
set_property DRIVE 8 [get_ports *fixed_io_ps*]
|
|
-set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk]
|
|
-set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb]
|
|
+set_property PACKAGE_PIN E7 [get_ports fixed_io_ps_clk]
|
|
+set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_porb]
|
|
|
|
set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*]
|
|
set_property SLEW FAST [get_ports *fixed_io_ddr_vr*]
|
|
-set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp]
|
|
-set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn]
|
|
+set_property PACKAGE_PIN H5 [get_ports fixed_io_ddr_vrp]
|
|
+set_property PACKAGE_PIN G5 [get_ports fixed_io_ddr_vrn]
|
|
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*]
|
|
set_property SLEW FAST [get_ports *ddr_ck*]
|
|
-set_property PACKAGE_PIN N3 [get_ports ddr_ck_p]
|
|
-set_property PACKAGE_PIN N2 [get_ports ddr_ck_n]
|
|
+set_property PACKAGE_PIN L2 [get_ports ddr_ck_p]
|
|
+set_property PACKAGE_PIN M2 [get_ports ddr_ck_n]
|
|
|
|
set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*]
|
|
set_property SLEW SLOW [get_ports *ddr_addr*]
|
|
-set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]]
|
|
-set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]]
|
|
-set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]]
|
|
-set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]]
|
|
-set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]]
|
|
-set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]]
|
|
-set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]]
|
|
-set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]]
|
|
-set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]]
|
|
-set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]]
|
|
-set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]]
|
|
-set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]]
|
|
-set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]]
|
|
-set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]]
|
|
-set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]]
|
|
+set_property PACKAGE_PIN N2 [get_ports ddr_addr[0]]
|
|
+set_property PACKAGE_PIN K2 [get_ports ddr_addr[1]]
|
|
+set_property PACKAGE_PIN M3 [get_ports ddr_addr[2]]
|
|
+set_property PACKAGE_PIN K3 [get_ports ddr_addr[3]]
|
|
+set_property PACKAGE_PIN M4 [get_ports ddr_addr[4]]
|
|
+set_property PACKAGE_PIN L1 [get_ports ddr_addr[5]]
|
|
+set_property PACKAGE_PIN L4 [get_ports ddr_addr[6]]
|
|
+set_property PACKAGE_PIN K4 [get_ports ddr_addr[7]]
|
|
+set_property PACKAGE_PIN K1 [get_ports ddr_addr[8]]
|
|
+set_property PACKAGE_PIN J4 [get_ports ddr_addr[9]]
|
|
+set_property PACKAGE_PIN F5 [get_ports ddr_addr[10]]
|
|
+set_property PACKAGE_PIN G4 [get_ports ddr_addr[11]]
|
|
+set_property PACKAGE_PIN E4 [get_ports ddr_addr[12]]
|
|
+set_property PACKAGE_PIN D4 [get_ports ddr_addr[13]]
|
|
+set_property PACKAGE_PIN F4 [get_ports ddr_addr[14]]
|
|
|
|
set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*]
|
|
set_property SLEW SLOW [get_ports *ddr_ba*]
|
|
-set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]]
|
|
-set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]]
|
|
-set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]]
|
|
+set_property PACKAGE_PIN L5 [get_ports ddr_ba[0]]
|
|
+set_property PACKAGE_PIN R4 [get_ports ddr_ba[1]]
|
|
+set_property PACKAGE_PIN J5 [get_ports ddr_ba[2]]
|
|
|
|
set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n]
|
|
set_property SLEW FAST [get_ports ddr_reset_n]
|
|
-set_property PACKAGE_PIN L4 [get_ports ddr_reset_n]
|
|
+set_property PACKAGE_PIN B4 [get_ports ddr_reset_n]
|
|
set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n]
|
|
set_property SLEW SLOW [get_ports ddr_cs_n]
|
|
-set_property PACKAGE_PIN R2 [get_ports ddr_cs_n]
|
|
+set_property PACKAGE_PIN N1 [get_ports ddr_cs_n]
|
|
set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n]
|
|
set_property SLEW SLOW [get_ports ddr_ras_n]
|
|
-set_property PACKAGE_PIN R6 [get_ports ddr_ras_n]
|
|
+set_property PACKAGE_PIN P4 [get_ports ddr_ras_n]
|
|
set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n]
|
|
set_property SLEW SLOW [get_ports ddr_cas_n]
|
|
-set_property PACKAGE_PIN R5 [get_ports ddr_cas_n]
|
|
+set_property PACKAGE_PIN P5 [get_ports ddr_cas_n]
|
|
set_property IOSTANDARD SSTL15 [get_ports ddr_we_n]
|
|
set_property SLEW SLOW [get_ports ddr_we_n]
|
|
-set_property PACKAGE_PIN R3 [get_ports ddr_we_n]
|
|
+set_property PACKAGE_PIN M5 [get_ports ddr_we_n]
|
|
set_property IOSTANDARD SSTL15 [get_ports ddr_cke]
|
|
set_property SLEW SLOW [get_ports ddr_cke]
|
|
-set_property PACKAGE_PIN L3 [get_ports ddr_cke]
|
|
+set_property PACKAGE_PIN N3 [get_ports ddr_cke]
|
|
set_property IOSTANDARD SSTL15 [get_ports ddr_odt]
|
|
set_property SLEW SLOW [get_ports ddr_odt]
|
|
-set_property PACKAGE_PIN K3 [get_ports ddr_odt]
|
|
+set_property PACKAGE_PIN N5 [get_ports ddr_odt]
|
|
|
|
set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]]
|
|
set_property SLEW FAST [get_ports *ddr_dq[*]]
|
|
-set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]]
|
|
-set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]]
|
|
-set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]]
|
|
-set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]]
|
|
-set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]]
|
|
-set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]]
|
|
-set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]]
|
|
-set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]]
|
|
-set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]]
|
|
-set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]]
|
|
-set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]]
|
|
-set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]]
|
|
-set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]]
|
|
-set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]]
|
|
+set_property PACKAGE_PIN C3 [get_ports ddr_dq[0]]
|
|
+set_property PACKAGE_PIN B3 [get_ports ddr_dq[1]]
|
|
+set_property PACKAGE_PIN A2 [get_ports ddr_dq[2]]
|
|
+set_property PACKAGE_PIN A4 [get_ports ddr_dq[3]]
|
|
+set_property PACKAGE_PIN D3 [get_ports ddr_dq[4]]
|
|
+set_property PACKAGE_PIN D1 [get_ports ddr_dq[5]]
|
|
+set_property PACKAGE_PIN C1 [get_ports ddr_dq[6]]
|
|
+set_property PACKAGE_PIN E1 [get_ports ddr_dq[7]]
|
|
+set_property PACKAGE_PIN E2 [get_ports ddr_dq[8]]
|
|
+set_property PACKAGE_PIN E3 [get_ports ddr_dq[9]]
|
|
+set_property PACKAGE_PIN G3 [get_ports ddr_dq[10]]
|
|
+set_property PACKAGE_PIN H3 [get_ports ddr_dq[11]]
|
|
+set_property PACKAGE_PIN J3 [get_ports ddr_dq[12]]
|
|
+set_property PACKAGE_PIN H2 [get_ports ddr_dq[13]]
|
|
set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]]
|
|
-set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]]
|
|
+set_property PACKAGE_PIN J1 [get_ports ddr_dq[15]]
|
|
set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]]
|
|
set_property SLEW FAST [get_ports *ddr_dm[*]]
|
|
-set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]]
|
|
-set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]]
|
|
+set_property PACKAGE_PIN A1 [get_ports ddr_dm[0]]
|
|
+set_property PACKAGE_PIN F1 [get_ports ddr_dm[1]]
|
|
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*]
|
|
set_property SLEW FAST [get_ports *ddr_dqs*]
|
|
set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]]
|
|
diff --git a/projects/pluto/system_project.tcl b/projects/pluto/system_project.tcl
|
|
index 89d81a44..fec220a1 100644
|
|
--- a/projects/pluto/system_project.tcl
|
|
+++ b/projects/pluto/system_project.tcl
|
|
@@ -3,7 +3,7 @@ source ../scripts/adi_env.tcl
|
|
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
|
|
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
|
|
|
-set p_device "xc7z010clg225-1"
|
|
+set p_device "xc7z010clg400-1"
|
|
adi_project pluto
|
|
|
|
adi_project_files pluto [list \
|