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plutosdr_fw_path
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Simplify the patch on Linux DTS

master
Howard Su 2021-04-24 15:43:47 +08:00
parent ce249ba162
commit 67ddd7498e
3 changed files with 40 additions and 319 deletions
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16
patches/hdl.diff
View File

@ -1,8 +1,8 @@
diff --git a/projects/pluto/system_bd.tcl b/projects/pluto/system_bd.tcl diff --git a/projects/pluto/system_bd.tcl b/projects/pluto/system_bd.tcl
index 8a9634b9a..72644e176 100644 index 8a9634b9..85c1bc28 100644
--- a/projects/pluto/system_bd.tcl --- a/projects/pluto/system_bd.tcl
+++ b/projects/pluto/system_bd.tcl +++ b/projects/pluto/system_bd.tcl
@@ -47,6 +47,11 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0 @@ -47,6 +47,12 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0 ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0
ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 17 ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 17
@ -11,10 +11,11 @@ index 8a9634b9a..72644e176 100644
+ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}
+ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53}
+
ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 0 ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 0
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 0 ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 0
ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1
@@ -54,16 +59,25 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13} @@ -54,16 +60,28 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 0 ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 0
ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE 1
@ -26,8 +27,10 @@ index 8a9634b9a..72644e176 100644
+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_SD0_IO "MIO 40 .. 45" +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_SD0_IO "MIO 40 .. 45"
+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_ENABLE 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_IO "MIO 47" +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_IO "MIO 47"
+ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_47_PULLUP {disabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_47_PULLUP {enabled}
+ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_47_SLEW {slow} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_47_SLEW {slow}
+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_POW_ENABLE 0
+ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_WP_ENABLE 0
+ +
ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0 ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1 ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1
@ -38,12 +41,13 @@ index 8a9634b9a..72644e176 100644
+ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO {MIO 46} +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO {MIO 46}
ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_46_SLEW {slow} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_46_SLEW {slow}
+ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_46_PULLUP {enabled}
+ +
ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1 ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1
ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE
ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_0_PULLUP {enabled} ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_0_PULLUP {enabled}
diff --git a/projects/pluto/system_constr.xdc b/projects/pluto/system_constr.xdc diff --git a/projects/pluto/system_constr.xdc b/projects/pluto/system_constr.xdc
index 67a9558cf..9bf4e924f 100644 index 67a9558c..9bf4e924 100644
--- a/projects/pluto/system_constr.xdc --- a/projects/pluto/system_constr.xdc
+++ b/projects/pluto/system_constr.xdc +++ b/projects/pluto/system_constr.xdc
@@ -1,69 +1,69 @@ @@ -1,69 +1,69 @@
@ -382,7 +386,7 @@ index 67a9558cf..9bf4e924f 100644
set_property SLEW FAST [get_ports *ddr_dqs*] set_property SLEW FAST [get_ports *ddr_dqs*]
set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]] set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]]
diff --git a/projects/pluto/system_project.tcl b/projects/pluto/system_project.tcl diff --git a/projects/pluto/system_project.tcl b/projects/pluto/system_project.tcl
index 89d81a448..fec220a11 100644 index 89d81a44..fec220a1 100644
--- a/projects/pluto/system_project.tcl --- a/projects/pluto/system_project.tcl
+++ b/projects/pluto/system_project.tcl +++ b/projects/pluto/system_project.tcl
@@ -3,7 +3,7 @@ source ../scripts/adi_env.tcl @@ -3,7 +3,7 @@ source ../scripts/adi_env.tcl

127
patches/linux.diff
View File

@ -1,5 +1,5 @@
diff --git a/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts b/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts diff --git a/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts b/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts
index 7aff4e197d0f..6eadb4e519d9 100644 index 7aff4e197d0f..5313336a30a4 100644
--- a/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts --- a/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts
+++ b/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts +++ b/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts
@@ -17,46 +17,6 @@ @@ -17,46 +17,6 @@
@ -61,7 +61,7 @@ index 7aff4e197d0f..6eadb4e519d9 100644
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
led0 { led0 {
@@ -92,3 +57,81 @@ @@ -92,3 +57,18 @@
}; };
}; };
}; };
@ -80,74 +80,12 @@ index 7aff4e197d0f..6eadb4e519d9 100644
+ pinctrl-names = "default"; + pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>; + pinctrl-0 = <&pinctrl_usb0_default>;
+}; +};
+ \ No newline at end of file
+&pinctrl0 {
+ pinctrl_gem0_default: gem0-default {
+ mux {
+ function = "ethernet0";
+ groups = "ethernet0_0_grp";
+ };
+
+ conf {
+ groups = "ethernet0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
+ low-power-enable;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio0";
+ groups = "mdio0_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO29", "MIO31", "MIO36";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
+ "MIO35", "MIO37", "MIO38", "MIO39";
+ bias-disable;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/zynq-pluto-sdr.dtsi b/arch/arm/boot/dts/zynq-pluto-sdr.dtsi diff --git a/arch/arm/boot/dts/zynq-pluto-sdr.dtsi b/arch/arm/boot/dts/zynq-pluto-sdr.dtsi
index 6cd0e41e5411..7759d862be1e 100644 index e936f48dbd73..bad6c46056a5 100644
--- a/arch/arm/boot/dts/zynq-pluto-sdr.dtsi --- a/arch/arm/boot/dts/zynq-pluto-sdr.dtsi
+++ b/arch/arm/boot/dts/zynq-pluto-sdr.dtsi +++ b/arch/arm/boot/dts/zynq-pluto-sdr.dtsi
@@ -40,8 +40,17 @@ @@ -40,8 +40,16 @@
}; };
@ -161,20 +99,13 @@ index 6cd0e41e5411..7759d862be1e 100644
&sdhci0 { &sdhci0 {
- status = "disabled"; - status = "disabled";
+ status = "okay"; + status = "okay";
+ pinctrl-names = "default"; + disable-wp;
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
}; };
&watchdog0 { &watchdog0 {
@@ -49,13 +58,35 @@ @@ -50,12 +58,29 @@
reset-on-timeout;
}; };
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
&usb0 { &usb0 {
- xlnx,phy-reset-gpio = <&gpio0 52 0>; - xlnx,phy-reset-gpio = <&gpio0 52 0>;
+ xlnx,phy-reset-gpio = <&gpio0 46 0>; + xlnx,phy-reset-gpio = <&gpio0 46 0>;
@ -203,7 +134,7 @@ index 6cd0e41e5411..7759d862be1e 100644
&qspi { &qspi {
status = "okay"; status = "okay";
is-dual = <0>; is-dual = <0>;
@@ -97,6 +128,18 @@ @@ -98,6 +123,18 @@
}; };
}; };
@ -222,7 +153,7 @@ index 6cd0e41e5411..7759d862be1e 100644
/ { / {
fpga_axi: fpga-axi@0 { fpga_axi: fpga-axi@0 {
compatible = "simple-bus"; compatible = "simple-bus";
@@ -186,6 +229,146 @@ @@ -187,6 +224,148 @@
}; };
}; };
@ -279,9 +210,11 @@ index 6cd0e41e5411..7759d862be1e 100644
+ conf-rx { + conf-rx {
+ pins = "MIO29", "MIO31", "MIO36"; + pins = "MIO29", "MIO31", "MIO36";
+ bias-high-impedance; + bias-high-impedance;
+ slew-rate = <0>; + };
+ io-standard = <1>; +
+ bias-disable; + conf-pull-up {
+ pins = "MIO46";
+ bias-pull-up;
+ }; + };
+ +
+ conf-tx { + conf-tx {
@ -309,7 +242,7 @@ index 6cd0e41e5411..7759d862be1e 100644
+ }; + };
+ +
+ conf-pull-none { + conf-pull-none {
+ pins = "MIO7", "MIO11", "MIO46"; + pins = "MIO7", "MIO11";
+ bias-disable; + bias-disable;
+ }; + };
+ }; + };
@ -370,7 +303,7 @@ index 6cd0e41e5411..7759d862be1e 100644
status = "okay"; status = "okay";
diff --git a/arch/arm/configs/zynq_pluto_defconfig b/arch/arm/configs/zynq_pluto_defconfig diff --git a/arch/arm/configs/zynq_pluto_defconfig b/arch/arm/configs/zynq_pluto_defconfig
index e00b680e8baa..7bd885f59489 100644 index ca72dd96a29d..01ed0ddd753d 100644
--- a/arch/arm/configs/zynq_pluto_defconfig --- a/arch/arm/configs/zynq_pluto_defconfig
+++ b/arch/arm/configs/zynq_pluto_defconfig +++ b/arch/arm/configs/zynq_pluto_defconfig
@@ -270,3 +270,15 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60 @@ -270,3 +270,15 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60
@ -389,31 +322,3 @@ index e00b680e8baa..7bd885f59489 100644
+CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_ARASAN=y
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 3b87b2e4486d..0d4602c59b75 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -1983,15 +1983,17 @@ static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
goto unlock;
}
- /* Make newly initialized descriptor visible to hardware */
- wmb();
- skb_tx_timestamp(skb);
-
- macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
-
if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
netif_stop_subqueue(dev, queue_index);
+ skb_tx_timestamp(skb);
+
+ if (!skb->xmit_more || __netif_subqueue_stopped(dev, queue_index)) {
+ /* Make newly initialized descriptor visible to hardware */
+ wmb();
+ macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
+ }
+
unlock:
spin_unlock_irqrestore(&bp->lock, flags);

216
patches/u-boot-xlnx.diff
View File

@ -1,5 +1,5 @@
diff --git a/arch/arm/dts/zynq-pluto-sdr.dts b/arch/arm/dts/zynq-pluto-sdr.dts diff --git a/arch/arm/dts/zynq-pluto-sdr.dts b/arch/arm/dts/zynq-pluto-sdr.dts
index c618d98b54..684826ebe6 100644 index c618d98b54..c318383554 100644
--- a/arch/arm/dts/zynq-pluto-sdr.dts --- a/arch/arm/dts/zynq-pluto-sdr.dts
+++ b/arch/arm/dts/zynq-pluto-sdr.dts +++ b/arch/arm/dts/zynq-pluto-sdr.dts
@@ -16,6 +16,7 @@ @@ -16,6 +16,7 @@
@ -10,186 +10,20 @@ index c618d98b54..684826ebe6 100644
}; };
memory { memory {
@@ -66,12 +67,167 @@ @@ -75,3 +76,8 @@
};
};
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
&usb0 {
status = "okay";
dr_mode = "host"; dr_mode = "host";
usb-phy = <&usb_phy0>; usb-phy = <&usb_phy0>;
+ pinctrl-names = "default"; };
+ pinctrl-0 = <&pinctrl_usb0_default>;
+};
+ +
+&sdhci0 { +&sdhci0 {
+ u-boot,dm-pre-reloc; + u-boot,dm-pre-reloc;
+ status = "okay"; + status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
};
+
+&pinctrl0 {
+ pinctrl_gem0_default: gem0-default {
+ mux {
+ function = "ethernet0";
+ groups = "ethernet0_0_grp";
+ };
+
+ conf {
+ groups = "ethernet0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
+ low-power-enable;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio0";
+ groups = "mdio0_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO29", "MIO31", "MIO36";
+ bias-high-impedance;
+ slew-rate = <0>;
+ io-standard = <1>;
+ bias-disable;
+ };
+
+ conf-tx {
+ pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
+ "MIO35", "MIO37", "MIO38", "MIO39";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio0_default: gpio0-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_7_grp", "gpio0_11_grp", "gpio0_14_grp", "gpio0_46_grp";
+ };
+
+ conf {
+ groups = "gpio0_7_grp", "gpio0_11_grp", "gpio0_14_grp", "gpio0_46_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-pull-up {
+ pins = "MIO14";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO7", "MIO11", "MIO46";
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_2_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_2_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "gpio0_47_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "gpio0_47_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_1_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_1_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO13";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO12";
+ bias-disable;
+ };
+ };
+}; +};
\ No newline at end of file \ No newline at end of file
diff --git a/configs/zynq_pluto_defconfig b/configs/zynq_pluto_defconfig diff --git a/configs/zynq_pluto_defconfig b/configs/zynq_pluto_defconfig
index 0daf46221e..9006b8bcf4 100644 index 0daf46221e..5991fa6cf7 100644
--- a/configs/zynq_pluto_defconfig --- a/configs/zynq_pluto_defconfig
+++ b/configs/zynq_pluto_defconfig +++ b/configs/zynq_pluto_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
+CONFIG_SYS_CONFIG_NAME="zynq_pluto"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_DEFAULT_DEVICE_TREE="zynq-pluto-sdr"
@@ -7,13 +7,14 @@ CONFIG_SPL=y @@ -7,13 +7,14 @@ CONFIG_SPL=y
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
@ -218,9 +52,8 @@ index 0daf46221e..9006b8bcf4 100644
+CONFIG_NAND_ARASAN=y +CONFIG_NAND_ARASAN=y
+CONFIG_DM_ETH=y +CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_GEM=y
\ No newline at end of file
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 50e93061a9..f7c2e010b8 100644 index c0e9a47b2b..39967684bd 100644
--- a/include/configs/zynq-common.h --- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h
@@ -257,7 +257,7 @@ @@ -257,7 +257,7 @@
@ -232,33 +65,12 @@ index 50e93061a9..f7c2e010b8 100644
"clear_reset_cause=mw f8000008 df0d && mw f8000258 00400000 && mw f8000004 767b\0" \ "clear_reset_cause=mw f8000008 df0d && mw f8000258 00400000 && mw f8000004 767b\0" \
"loadbootenv=load mmc 0 ${loadbootenv_addr} ${bootenv}\0" \ "loadbootenv=load mmc 0 ${loadbootenv_addr} ${bootenv}\0" \
"importbootenv=echo Importing environment from SD ...; " \ "importbootenv=echo Importing environment from SD ...; " \
diff --git a/include/configs/zynq_pluto.h b/include/configs/zynq_pluto.h @@ -269,7 +269,7 @@
new file mode 100644 "fi; " \
index 0000000000..8c0e74d770 "fi; \0" \
--- /dev/null "refclk_source=internal\0" \
+++ b/include/configs/zynq_pluto.h - "mode=1r1t\0" \
@@ -0,0 +1,24 @@ + "mode=2r2t\0" \
+/* "adi_loadvals_pluto=if test -n \"${ad936x_ext_refclk}\" && test ! -n \"${ad936x_skip_ext_refclk}\"; then " \
+ * (C) Copyright 2013 Xilinx, Inc. "fdt set /clocks/clock@0 clock-frequency ${ad936x_ext_refclk}; " \
+ * "fi; " \
+ * Configuration settings for the PlutoSDR Boards
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_PLUTOSDR_H
+#define __CONFIG_ZYNQ_PLUTOSDR_H
+
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_EEPROM
+#define CONFIG_ZYNQ_USB
+#define CONFIG_DFU_SF
+
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR 0
+#define CONFIG_HAS_ETH0
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_PLUTOSDR_H */