257 lines
6.9 KiB
Verilog
257 lines
6.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_lvds_in (
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// data interface
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rx_clk,
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rx_data_in_p,
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rx_data_in_n,
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rx_data_p,
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rx_data_n,
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// delay-data interface
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up_clk,
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up_dld,
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up_dwdata,
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up_drdata,
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// delay-cntrl interface
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delay_clk,
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delay_rst,
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delay_locked);
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// parameters
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parameter SINGLE_ENDED = 0;
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parameter DEVICE_TYPE = 0;
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parameter IODELAY_CTRL = 0;
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parameter IODELAY_GROUP = "dev_if_delay_group";
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localparam VIRTEX7 = 0;
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localparam VIRTEX6 = 1;
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localparam ULTRASCALE = 2;
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// data interface
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input rx_clk;
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input rx_data_in_p;
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input rx_data_in_n;
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output rx_data_p;
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output rx_data_n;
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// delay-data interface
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input up_clk;
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input up_dld;
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input [ 4:0] up_dwdata;
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output [ 4:0] up_drdata;
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// delay-cntrl interface
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input delay_clk;
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input delay_rst;
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output delay_locked;
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// internal registers
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reg rx_data_n;
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// internal signals
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wire rx_data_n_s;
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wire rx_data_ibuf_s;
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wire rx_data_idelay_s;
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wire [ 8:0] up_drdata_s;
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// delay controller
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generate
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if (IODELAY_CTRL == 1) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYCTRL i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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end else begin
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assign delay_locked = 1'b1;
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end
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endgenerate
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// receive data interface, ibuf -> idelay -> iddr
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generate
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if (SINGLE_ENDED == 1) begin
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IBUF i_rx_data_ibuf (
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.I (rx_data_in_p),
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.O (rx_data_ibuf_s));
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end else begin
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IBUFDS i_rx_data_ibuf (
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.I (rx_data_in_p),
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.IB (rx_data_in_n),
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.O (rx_data_ibuf_s));
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end
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endgenerate
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generate
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if (DEVICE_TYPE == VIRTEX6) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IODELAYE1 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("I"),
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.HIGH_PERFORMANCE_MODE ("TRUE"),
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.IDELAY_TYPE ("VAR_LOADABLE"),
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.IDELAY_VALUE (0),
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.ODELAY_TYPE ("FIXED"),
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.ODELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.SIGNAL_PATTERN ("DATA"))
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i_rx_data_idelay (
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.T (1'b1),
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.CE (1'b0),
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.INC (1'b0),
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.CLKIN (1'b0),
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.DATAIN (1'b0),
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.ODATAIN (1'b0),
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.CINVCTRL (1'b0),
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.C (up_clk),
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.RST (up_dld),
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.CNTVALUEIN (up_dwdata),
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.CNTVALUEOUT (up_drdata));
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end
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endgenerate
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generate
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if (DEVICE_TYPE == VIRTEX7) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("IDATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.IDELAY_TYPE ("VAR_LOAD"),
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.IDELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA"))
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i_rx_data_idelay (
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.CE (1'b0),
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.INC (1'b0),
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.DATAIN (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (up_clk),
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.LD (up_dld),
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.CNTVALUEIN (up_dwdata),
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.CNTVALUEOUT (up_drdata));
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end
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endgenerate
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generate
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if (DEVICE_TYPE == ULTRASCALE) begin
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assign up_drdata = up_drdata_s[8:4];
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE3 #(
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.DELAY_SRC ("IDATAIN"),
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.DELAY_TYPE ("VAR_LOAD"),
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.REFCLK_FREQUENCY (200.0),
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.DELAY_FORMAT ("COUNT"))
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i_rx_data_idelay (
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.CASC_RETURN (1'b0),
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.CASC_IN (1'b0),
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.CASC_OUT (),
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.CE (1'b0),
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.CLK (up_clk),
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.INC (1'b0),
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.LOAD (up_dld),
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.CNTVALUEIN ({up_dwdata, 4'd0}),
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.CNTVALUEOUT (up_drdata_s),
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.DATAIN (1'b0),
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.RST (1'b0),
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.EN_VTC (~up_dld));
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end
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endgenerate
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generate
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if (DEVICE_TYPE == ULTRASCALE) begin
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IDDRE1 #(
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.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
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i_rx_data_iddr (
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.R (1'b0),
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.C (rx_clk),
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.CB (~rx_clk),
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.D (rx_data_idelay_s),
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.Q1 (rx_data_p),
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.Q2 (rx_data_n_s));
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end else begin
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IDDR #(
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.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
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.INIT_Q1 (1'b0),
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.INIT_Q2 (1'b0),
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.SRTYPE ("ASYNC"))
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i_rx_data_iddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (rx_clk),
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.D (rx_data_idelay_s),
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.Q1 (rx_data_p),
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.Q2 (rx_data_n_s));
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end
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endgenerate
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always @(posedge rx_clk) begin
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rx_data_n <= rx_data_n_s;
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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