2e173201d4
Use the sys_dma_clk clock module for clock and reset signals of the data path, rather than using the A10GX specific sys_ddr3_cntrl signals. This enables compatibility for all Altera/Intel platforms. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| a10gx | ||
| common | ||
| kc705 | ||
| kcu105 | ||
| vc707 | ||
| zc706 | ||
| zcu102 | ||
| Makefile | ||