207 lines
6.6 KiB
Verilog
207 lines
6.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// this is a sine function (approximate), the basic idea is to approximate sine as a
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// polynomial function (there are a lot of stuff about this on the web)
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`timescale 1ns/100ps
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module ad_dds_sine #(
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parameter DELAY_DATA_WIDTH = 16) (
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// sine = sin(angle)
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input clk,
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input [15:0] angle,
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output [15:0] sine,
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input [(DELAY_DATA_WIDTH-1):0] ddata_in,
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output [(DELAY_DATA_WIDTH-1):0] ddata_out);
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// internal registers
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reg [33:0] s1_data_p = 'd0;
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reg [33:0] s1_data_n = 'd0;
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reg [15:0] s1_angle = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] s1_ddata = 'd0;
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reg [18:0] s2_data_0 = 'd0;
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reg [18:0] s2_data_1 = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] s2_ddata = 'd0;
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reg [18:0] s3_data = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] s3_ddata = 'd0;
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reg [33:0] s4_data2_p = 'd0;
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reg [33:0] s4_data2_n = 'd0;
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reg [16:0] s4_data1_p = 'd0;
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reg [16:0] s4_data1_n = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] s4_ddata = 'd0;
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reg [16:0] s5_data2_0 = 'd0;
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reg [16:0] s5_data2_1 = 'd0;
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reg [16:0] s5_data1 = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] s5_ddata = 'd0;
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reg [16:0] s6_data2 = 'd0;
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reg [16:0] s6_data1 = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] s6_ddata = 'd0;
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reg [33:0] s7_data = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] s7_ddata = 'd0;
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reg [15:0] sine_int = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] ddata_out_int = 'd0;
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// internal signals
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wire [15:0] angle_s;
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wire [33:0] s1_data_s;
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wire [(DELAY_DATA_WIDTH-1):0] s1_ddata_s;
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wire [15:0] s1_angle_s;
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wire [33:0] s4_data2_s;
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wire [(DELAY_DATA_WIDTH-1):0] s4_ddata_s;
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wire [16:0] s4_data1_s;
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wire [33:0] s7_data2_s;
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wire [33:0] s7_data1_s;
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wire [(DELAY_DATA_WIDTH-1):0] s7_ddata_s;
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// make angle 2's complement
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assign angle_s = {~angle[15], angle[14:0]};
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// level 1 - intermediate
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ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+16)) i_mul_s1 (
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.clk (clk),
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.data_a ({angle_s[15], angle_s}),
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.data_b ({angle_s[15], angle_s}),
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.data_p (s1_data_s),
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.ddata_in ({ddata_in, angle_s}),
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.ddata_out ({s1_ddata_s, s1_angle_s}));
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// 2's complement versions
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always @(posedge clk) begin
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s1_data_p <= s1_data_s;
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s1_data_n <= ~s1_data_s + 1'b1;
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s1_angle <= s1_angle_s;
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s1_ddata <= s1_ddata_s;
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end
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// select partial products
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always @(posedge clk) begin
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s2_data_0 <= (s1_angle[15] == 1'b0) ? s1_data_n[31:13] : s1_data_p[31:13];
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s2_data_1 <= {s1_angle[15], s1_angle[15:0], 2'b00};
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s2_ddata <= s1_ddata;
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end
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// unit-sine
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always @(posedge clk) begin
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s3_data <= s2_data_0 + s2_data_1;
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s3_ddata <= s2_ddata;
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end
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// level 2 - final
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ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s2 (
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.clk (clk),
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.data_a (s3_data[16:0]),
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.data_b (s3_data[16:0]),
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.data_p (s4_data2_s),
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.ddata_in ({s3_ddata, s3_data[16:0]}),
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.ddata_out ({s4_ddata_s, s4_data1_s}));
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// 2's complement versions
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always @(posedge clk) begin
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s4_data2_p <= s4_data2_s;
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s4_data2_n <= ~s4_data2_s + 1'b1;
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s4_data1_p <= s4_data1_s;
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s4_data1_n <= ~s4_data1_s + 1'b1;
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s4_ddata <= s4_ddata_s;
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end
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// select partial products
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always @(posedge clk) begin
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s5_data2_0 <= (s4_data1_p[16] == 1'b1) ? s4_data2_n[31:15] : s4_data2_p[31:15];
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s5_data2_1 <= s4_data1_n;
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s5_data1 <= s4_data1_p;
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s5_ddata <= s4_ddata;
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end
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// corrected-sine
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always @(posedge clk) begin
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s6_data2 <= s5_data2_0 + s5_data2_1;
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s6_data1 <= s5_data1;
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s6_ddata <= s5_ddata;
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end
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// full-scale
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ad_mul #(.DELAY_DATA_WIDTH(1)) i_mul_s3_2 (
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.clk (clk),
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.data_a (s6_data2),
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.data_b (17'h1d08),
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.data_p (s7_data2_s),
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.ddata_in (1'b0),
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.ddata_out ());
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ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_s3_1 (
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.clk (clk),
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.data_a (s6_data1),
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.data_b (17'h7fff),
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.data_p (s7_data1_s),
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.ddata_in (s6_ddata),
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.ddata_out (s7_ddata_s));
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// corrected sum
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always @(posedge clk) begin
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s7_data <= s7_data2_s + s7_data1_s;
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s7_ddata <= s7_ddata_s;
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end
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// output registers
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assign sine = sine_int;
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assign ddata_out = ddata_out_int;
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always @(posedge clk) begin
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sine_int <= s7_data[30:15];
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ddata_out_int <= s7_ddata;
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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