fd89458708
There will rarely be concurrent access to the peripheral control bus interconnect, so there is no need to optimize for performace. Setting the interconnect strategy to minimize area can reduce the resource usage by ~90%. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md |
README.md
hdl
Analog Devices HDL libraries and projects
First time users, it is highly recommended to go through our HDL user guide at the following url:
http://wiki.analog.com/resources/fpga/docs/hdl
For support please visit our FPGA Reference Designs Support Community on EngineerZone: