122 lines
4.4 KiB
Verilog
122 lines
4.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// A simple asymetric memory. The write and read memory space must have the same size.
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// 2^A_ADDRESS_WIDTH * A_DATA_WIDTH == 2^B_ADDRESS_WIDTH * B_DATA_WIDTH
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`timescale 1ns/100ps
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module ad_mem_asym #(
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// parameters
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parameter A_ADDRESS_WIDTH = 8,
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parameter A_DATA_WIDTH = 256,
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parameter B_ADDRESS_WIDTH = 10,
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parameter B_DATA_WIDTH = 64) (
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// write interface
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input clka,
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input wea,
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input [A_ADDRESS_WIDTH-1:0] addra,
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input [A_DATA_WIDTH-1:0] dina,
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// read interface
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input clkb,
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input [B_ADDRESS_WIDTH-1:0] addrb,
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output [B_DATA_WIDTH-1:0] doutb);
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// broken altera-hdl-inference, direct instantiation
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altera_syncram #(
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.lpm_type ("altera_syncram"),
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.operation_mode ("DUAL_PORT"),
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.ram_block_type ("M20K"),
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.widthad_a (A_ADDRESS_WIDTH),
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.width_a (A_DATA_WIDTH),
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.numwords_a (2**A_ADDRESS_WIDTH),
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.widthad_b (B_ADDRESS_WIDTH),
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.width_b (B_DATA_WIDTH),
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.numwords_b (2**B_ADDRESS_WIDTH),
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.intended_device_family ("Arria 10"),
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.clock_enable_input_a ("BYPASS"),
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.clock_enable_input_b ("BYPASS"),
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.clock_enable_output_b ("BYPASS"),
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.address_aclr_b ("NONE"),
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.outdata_aclr_b ("NONE"),
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.outdata_sclr_b ("NONE"),
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.address_reg_b ("CLOCK1"),
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.outdata_reg_b ("CLOCK1"),
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.power_up_uninitialized ("FALSE"),
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.width_byteena_a (1))
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i_alt_mem (
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.aclr0 (1'b0),
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.clock0 (clka),
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.address_a (addra),
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.wren_a (wea),
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.data_a (dina),
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.rden_a (1'b1),
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.q_a (),
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.aclr1 (1'b0),
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.clock1 (clkb),
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.address_b (addrb),
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.wren_b (1'b0),
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.data_b ('d0),
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.rden_b (1'b1),
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.q_b (doutb),
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.address2_a (1'b1),
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.address2_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.eccencbypass (1'b0),
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.eccencparity (8'b0),
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.eccstatus (),
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.sclr (1'b0));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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