Iulia Moldovan 5c9b271f3a Fix error regarding hierarchy that Vivado misses ... * Solution from here: https://support.xilinx.com/s/article/69320?language=en_US * Added in: * util_cdc * util_cic * jesd204_rx/tx * util_upack2 * axi_jesd204_common: used in axi_jesd204_rx/tx * axi_jesd204_rx/tx * jesd_common Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>		2023-08-01 18:12:40 +03:00
..
Makefile	library & projects: Update Makefiles	2023-01-27 11:54:05 +02:00
axi_jesd204_rx.v	axi_jesd204: Cleanup unused parameter	2022-08-25 12:35:42 +03:00
axi_jesd204_rx_constr.sdc	jesd204: Intel: NP12 support	2021-02-05 15:24:15 +02:00
axi_jesd204_rx_constr.xdc	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
axi_jesd204_rx_hw.tcl	scripts: Merge adi_env.tcl into a single file	2022-08-08 13:52:54 +03:00
axi_jesd204_rx_ip.tcl	Fix error regarding hierarchy that Vivado misses	2023-08-01 18:12:40 +03:00
axi_jesd204_rx_ooc.ttcl	jesd204/axi_jesd204: Complete clock definitions in out of context mode	2021-05-14 15:39:40 +03:00
jesd204_up_ilas_mem.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
jesd204_up_rx.v	axi_jesd204: Cleanup unused parameter	2022-08-25 12:35:42 +03:00
jesd204_up_rx_lane.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00