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altera
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mult-macro: use primitive parameters
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2015-08-20 13:54:16 -04:00 |
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ad_addsub.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_axi_ip_constr.sdc
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dac/adc- make common instances
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2015-08-21 14:41:09 -04:00 |
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ad_axi_ip_constr.xdc
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ip-constr- register name changes
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2015-08-27 11:18:00 -04:00 |
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ad_axis_dma_rx.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_axis_dma_tx.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_axis_inf_rx.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_csc_1.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_csc_1_add.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_csc_1_mul.v
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library: Fixed changes related to parameters
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2015-08-20 18:13:54 +03:00 |
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ad_csc_CrYCb2RGB.v
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imageon_zc706: Updates and fixes
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2015-03-27 18:57:32 +02:00 |
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ad_csc_RGB2CrYCb.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_datafmt.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_dcfilter.v
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common library: Registered dc_filter and iq_correction coefficients
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2015-09-16 14:24:18 +03:00 |
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ad_dds.v
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ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block
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2015-10-09 13:43:14 +03:00 |
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ad_dds_1.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_dds_sine.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_gt_channel.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_gt_channel_1.v
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up_gt: separate pll resets to tx/rx
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2015-10-02 13:58:30 -04:00 |
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ad_gt_common.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_gt_common_1.v
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up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address
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2015-09-29 14:19:52 +03:00 |
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ad_gt_es.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_gt_es_axi.v
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axi_jesd_gt- per lane split-up
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2015-08-13 13:03:51 -04:00 |
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ad_iobuf.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_iqcor.v
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common library: Registered dc_filter and iq_correction coefficients
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2015-09-16 14:24:18 +03:00 |
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ad_jesd_align.v
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jesd-align-- xilinx/altera merge
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2015-07-21 10:57:00 -04:00 |
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ad_lvds_clk.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_lvds_in.v
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ad_lvds_in: Add single ended option
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2015-11-13 12:13:09 +02:00 |
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ad_lvds_out.v
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common/ad_lvds_out- add single ended
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2015-08-27 11:41:47 -04:00 |
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ad_mem.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_mem_asym.v
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common: Allow for the memory to be also symetrical
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2015-11-04 13:28:02 +02:00 |
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ad_mmcm_drp.v
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library: Axi_clkgen, added register for controlling the source clock.
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2015-11-25 11:16:32 +02:00 |
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ad_mul.v
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library: Fixed changes related to parameters
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2015-08-20 18:13:54 +03:00 |
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ad_mul_u16.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_pnmon.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_rst.v
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library: ad_rst, added comment so that the registers are not minimized away
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2015-11-24 10:33:38 +02:00 |
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ad_serdes_clk.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_serdes_in.v
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library: Fixed changes related to parameters
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2015-08-20 18:13:54 +03:00 |
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ad_serdes_out.v
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library: Fixed changes related to parameters
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2015-08-20 18:13:54 +03:00 |
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ad_ss_422to444.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_ss_444to422.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_tdd_control.v
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ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received
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2015-11-24 15:15:53 +02:00 |
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ad_tdd_sync.v
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ad_tdd_sync: Fix reset value of the pulse_counter
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2015-11-13 18:31:24 +02:00 |
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axi_ctrlif.vhd
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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axi_streaming_dma_rx_fifo.vhd
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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axi_streaming_dma_tx_fifo.vhd
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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dma_fifo.vhd
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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pl330_dma_fifo.vhd
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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sync_bits.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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sync_gray.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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up_adc_channel.v
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dac/adc- make common instances
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2015-08-21 14:41:26 -04:00 |
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up_adc_common.v
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dac/adc- make common instances
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2015-08-21 14:41:30 -04:00 |
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up_axi.v
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up_axi- writes dropped by delayed w-responses
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2016-09-14 17:35:01 +03:00 |
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up_axis_dma_rx.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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up_axis_dma_tx.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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up_clkgen.v
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library: Axi_clkgen, added register for controlling the source clock.
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2015-11-25 11:16:32 +02:00 |
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up_clock_mon.v
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common/up_- change to asynchronous resets
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2015-08-13 13:03:51 -04:00 |
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up_dac_channel.v
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dac/adc- make common instances
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2015-08-21 14:41:35 -04:00 |
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up_dac_common.v
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dac/adc- make common instances
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2015-08-21 14:41:39 -04:00 |
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up_delay_cntrl.v
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up_delay_cntrl- cosmetics
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2015-08-28 13:16:18 -04:00 |
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up_drp_cntrl.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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up_gt.v
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up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address
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2015-09-29 14:19:52 +03:00 |
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up_gt_channel.v
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library/common- reset fix
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2015-10-23 14:32:35 -04:00 |
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up_hdmi_rx.v
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axi_hdmi_rx: Update constraint file and fix reset line
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2015-09-29 18:49:30 +03:00 |
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up_hdmi_tx.v
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axi_hdmi_tx: Upgrade hdmi clipping process
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2016-04-12 22:01:07 +03:00 |
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up_pmod.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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up_tdd_cntrl.v
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axi_ad9361: Delete the old sync generator from the core
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2015-11-11 11:06:19 +02:00 |
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up_xcvr.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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up_xfer_cntrl.v
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common/up_- change to asynchronous resets
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2015-08-13 13:03:51 -04:00 |
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up_xfer_status.v
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common/up_- change to asynchronous resets
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2015-08-13 13:03:51 -04:00 |
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