Istvan Csomortani fa32ea8f1f util_dacfifo: Fix the reset logic of the module ... Both the DMA and DAC side should be in reset at the positive edge of the dma_xfer_req, so we can re-initialize the buffer.		2018-10-11 16:57:30 +03:00
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Makefile	util_dacfifo: Update the bypass logic	2018-10-11 16:57:30 +03:00
util_dacfifo.v	util_dacfifo: Fix the reset logic of the module	2018-10-11 16:57:30 +03:00
util_dacfifo_bypass.v	util_dacfifo_bypass: The FIFO in this module is for CDC only, no need to have a large depth	2018-10-11 16:57:30 +03:00
util_dacfifo_constr.sdc	util_dacfifo: Fix the reset logic of the module	2018-10-11 16:57:30 +03:00
util_dacfifo_constr.xdc	util_dacfifo: Fix the reset logic of the module	2018-10-11 16:57:30 +03:00
util_dacfifo_hw.tcl	util_dacfifo: Fix the reset logic of the module	2018-10-11 16:57:30 +03:00
util_dacfifo_ip.tcl	util_dacfifo: Update the bypass logic	2018-10-11 16:57:30 +03:00