Filip Gherman 1ae375f4fb ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy ... - Added an utility buffer in order to generate the 50Mhz DRP clock. - 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze. Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>		2022-05-27 00:48:34 +03:00
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Makefile	ad_quadmxfe1_ebz: Initial version	2021-11-10 14:03:34 +02:00
system_bd.tcl	ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy	2022-05-27 00:48:34 +03:00
system_constr.xdc	ad_quadmxfe1_ebz: Refactor MxFE GPIOs	2022-05-11 18:09:08 +03:00
system_project.tcl	ad_quadmxfe1_ebz: Update parameter description	2022-03-11 13:16:22 +02:00
system_top.v	ad_quadmxfe1_ebz: Refactor MxFE GPIOs	2022-05-11 18:09:08 +03:00
timing_constr.xdc	ad_quadmxfe1_ebz: Initial version	2021-11-10 14:03:34 +02:00