301 lines
13 KiB
Tcl
301 lines
13 KiB
Tcl
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# create board design
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# default ports
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart_0
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 eth1_mdio
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth1_rgmii
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create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
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create_bd_port -dir O eth1_link_status
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create_bd_port -dir O eth1_duplex_status
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create_bd_port -dir O -type clk eth1_refclk
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create_bd_port -dir O -type clk eth1_125mclk
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create_bd_port -dir O -type clk eth1_25mclk
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create_bd_port -dir O -type clk eth1_2m5clk
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create_bd_port -dir I -type intr eth1_intn
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create_bd_port -dir O -from 1 -to 0 eth1_clock_speed
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create_bd_port -dir O -from 1 -to 0 eth1_speed_mode
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create_bd_port -dir O spi0_csn_2_o
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create_bd_port -dir O spi0_csn_1_o
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create_bd_port -dir O spi0_csn_0_o
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create_bd_port -dir I spi0_csn_i
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create_bd_port -dir I spi0_clk_i
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create_bd_port -dir O spi0_clk_o
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create_bd_port -dir I spi0_sdo_i
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create_bd_port -dir O spi0_sdo_o
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create_bd_port -dir I spi0_sdi_i
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create_bd_port -dir O spi1_csn_2_o
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create_bd_port -dir O spi1_csn_1_o
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create_bd_port -dir O spi1_csn_0_o
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create_bd_port -dir I spi1_csn_i
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create_bd_port -dir I spi1_clk_i
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create_bd_port -dir O spi1_clk_o
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create_bd_port -dir I spi1_sdo_i
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create_bd_port -dir O spi1_sdo_o
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create_bd_port -dir I spi1_sdi_i
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create_bd_port -dir I -from 63 -to 0 gpio_i
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create_bd_port -dir O -from 63 -to 0 gpio_o
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create_bd_port -dir O -from 63 -to 0 gpio_t
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# hdmi interface
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create_bd_port -dir O hdmi_out_clk
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create_bd_port -dir O hdmi_hsync
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create_bd_port -dir O hdmi_vsync
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create_bd_port -dir O hdmi_data_e
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create_bd_port -dir O -from 15 -to 0 hdmi_data
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# i2s
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set i2s_mclk [create_bd_port -dir O -type clk i2s_mclk]
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set i2s_bclk [create_bd_port -dir O i2s_bclk]
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set i2s_lrclk [create_bd_port -dir O i2s_lrclk]
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set i2s_sdata_out [create_bd_port -dir O i2s_sdata_out]
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set i2s_sdata_in [create_bd_port -dir I i2s_sdata_in]
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# otg
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set otg_vbusoc [create_bd_port -dir I otg_vbusoc]
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# spdif audio
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create_bd_port -dir O spdif
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# interrupts
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create_bd_port -dir I -type intr ps_intr_00
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create_bd_port -dir I -type intr ps_intr_01
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create_bd_port -dir I -type intr ps_intr_02
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create_bd_port -dir I -type intr ps_intr_03
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create_bd_port -dir I -type intr ps_intr_04
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create_bd_port -dir I -type intr ps_intr_05
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create_bd_port -dir I -type intr ps_intr_06
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create_bd_port -dir I -type intr ps_intr_07
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create_bd_port -dir I -type intr ps_intr_08
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create_bd_port -dir I -type intr ps_intr_09
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create_bd_port -dir I -type intr ps_intr_10
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create_bd_port -dir I -type intr ps_intr_11
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create_bd_port -dir I -type intr ps_intr_12
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create_bd_port -dir I -type intr ps_intr_13
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# instance: sys_ps7
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set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
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source $ad_hdl_dir/projects/common/rfsom/rfsom_system_ps7.tcl
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set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
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set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
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set sys_rgmii [create_bd_cell -type ip -vlnv xilinx.com:ip:gmii_to_rgmii:3.0 sys_rgmii]
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set_property -dict [list CONFIG.SupportLevel {Include_Shared_Logic_in_Core}] $sys_rgmii
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set sys_rgmii_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rgmii_rstgen]
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set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rgmii_rstgen
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set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
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set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
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set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
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# hdmi peripherals
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set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
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set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
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set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
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set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
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# audio peripherals
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set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
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set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
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set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
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set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
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set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
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set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
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set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
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set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_i2s_adi
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set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi
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# system reset/clock definitions
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ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
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ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
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# interface connections
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ad_connect ddr sys_ps7/DDR
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ad_connect gpio_i sys_ps7/GPIO_I
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ad_connect gpio_o sys_ps7/GPIO_O
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ad_connect gpio_t sys_ps7/GPIO_T
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ad_connect fixed_io sys_ps7/FIXED_IO
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ad_connect iic_main axi_iic_main/iic
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ad_connect sys_200m_clk axi_hdmi_clkgen/clk
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ad_connect sys_ps7/UART_0 uart_0
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ad_connect sys_ps7/MDIO_ETHERNET_1 sys_rgmii/MDIO_GEM
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ad_connect sys_ps7/GMII_ETHERNET_1 sys_rgmii/GMII
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ad_connect sys_rgmii/MDIO_PHY eth1_mdio
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ad_connect sys_rgmii/RGMII eth1_rgmii
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ad_connect sys_rgmii/ref_clk_out eth1_refclk
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ad_connect sys_rgmii/gmii_clk_125m_out eth1_125mclk
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ad_connect sys_rgmii/gmii_clk_25m_out eth1_25mclk
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ad_connect sys_rgmii/gmii_clk_2_5m_out eth1_2m5clk
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ad_connect sys_rgmii/link_status eth1_link_status
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ad_connect sys_rgmii/duplex_status eth1_duplex_status
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ad_connect sys_rgmii/clock_speed eth1_clock_speed
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ad_connect sys_rgmii/speed_mode eth1_speed_mode
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ad_connect sys_ps7/ENET1_EXT_INTIN eth1_intn
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ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
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ad_connect sys_logic_inv/Op1 otg_vbusoc
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ad_connect sys_200m_clk sys_rgmii_rstgen/slowest_sync_clk
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ad_connect sys_200m_clk sys_rgmii/clkin
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ad_connect sys_rgmii_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
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ad_connect sys_rgmii_rstgen/peripheral_reset sys_rgmii/tx_reset
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ad_connect sys_rgmii_rstgen/peripheral_reset sys_rgmii/rx_reset
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# spi connections
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ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
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ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
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ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
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ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
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ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
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ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
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ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
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ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
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ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
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ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
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ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
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ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
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ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
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ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
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ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
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ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
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ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
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ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
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# hdmi
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ad_connect sys_cpu_clk axi_hdmi_clkgen/drp_clk
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ad_connect sys_cpu_clk axi_hdmi_core/m_axis_mm2s_clk
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ad_connect sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
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ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
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ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
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ad_connect axi_hdmi_core/hdmi_16_hsync hdmi_hsync
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ad_connect axi_hdmi_core/hdmi_16_vsync hdmi_vsync
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ad_connect axi_hdmi_core/hdmi_16_data_e hdmi_data_e
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ad_connect axi_hdmi_core/hdmi_16_data hdmi_data
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ad_connect axi_hdmi_core/m_axis_mm2s_tvalid axi_hdmi_dma/m_axis_mm2s_tvalid
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ad_connect axi_hdmi_core/m_axis_mm2s_tdata axi_hdmi_dma/m_axis_mm2s_tdata
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ad_connect axi_hdmi_core/m_axis_mm2s_tkeep axi_hdmi_dma/m_axis_mm2s_tkeep
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ad_connect axi_hdmi_core/m_axis_mm2s_tlast axi_hdmi_dma/m_axis_mm2s_tlast
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ad_connect axi_hdmi_core/m_axis_mm2s_tready axi_hdmi_dma/m_axis_mm2s_tready
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ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_dma/mm2s_fsync
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ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_core/m_axis_mm2s_fsync_ret
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# spdif audio
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ad_connect sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK
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ad_connect sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
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ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
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ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
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ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
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ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
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ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
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ad_connect spdif axi_spdif_tx_core/spdif_tx_o
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# i2s audio
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ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
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ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA2_ACLK
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
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ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
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ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
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ad_connect sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
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ad_connect sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
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ad_connect sys_audio_clkgen/clk_out1 i2s_mclk
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ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
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ad_connect i2s_bclk axi_i2s_adi/BCLK_O
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ad_connect i2s_lrclk axi_i2s_adi/LRCLK_O
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ad_connect i2s_sdata_out axi_i2s_adi/SDATA_O
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ad_connect i2s_sdata_in axi_i2s_adi/SDATA_I
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# interrupts
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ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
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ad_connect sys_concat_intc/In15 axi_hdmi_dma/mm2s_introut
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ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
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ad_connect sys_concat_intc/In13 ps_intr_13
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ad_connect sys_concat_intc/In12 ps_intr_12
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ad_connect sys_concat_intc/In11 ps_intr_11
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ad_connect sys_concat_intc/In10 ps_intr_10
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ad_connect sys_concat_intc/In9 ps_intr_09
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ad_connect sys_concat_intc/In8 ps_intr_08
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ad_connect sys_concat_intc/In7 ps_intr_07
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ad_connect sys_concat_intc/In6 ps_intr_06
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ad_connect sys_concat_intc/In5 ps_intr_05
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ad_connect sys_concat_intc/In4 ps_intr_04
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ad_connect sys_concat_intc/In3 ps_intr_03
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ad_connect sys_concat_intc/In2 ps_intr_02
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ad_connect sys_concat_intc/In1 ps_intr_01
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ad_connect sys_concat_intc/In0 ps_intr_00
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# interconnects
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ad_cpu_interconnect 0x41600000 axi_iic_main
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ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
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ad_cpu_interconnect 0x43000000 axi_hdmi_dma
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ad_cpu_interconnect 0x70e00000 axi_hdmi_core
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ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
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ad_cpu_interconnect 0x77600000 axi_i2s_adi
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ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
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ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
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