pluto_hdl_adi/projects/ad9081_fmca_ebz/vcu118/timing_constr.xdc

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# Primary clock definitions
# refclk and refclk_replica are connect to the same source on the PCB
create_clock -name refclk -period 4 [get_ports fpga_refclk_in_p]
create_clock -name refclk_replica -period 4 [get_ports fpga_refclk_in_replica_p]
# device clock
create_clock -name tx_device_clk -period 4 [get_ports clkin6_p]
create_clock -name rx_device_clk -period 4 [get_ports clkin8_p]
# Constraint SYSREFs
# Assumption is that REFCLK and SYSREF have similar propagation delay,
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
set_input_delay -clock [get_clocks tx_device_clk] \
[get_property PERIOD [get_clocks tx_device_clk]] \
[get_ports {sysref2_*}]