69 lines
2.8 KiB
Verilog
69 lines
2.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_fir_dec (
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input aclk,
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input s_axis_data_tvalid,
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output s_axis_data_tready,
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input [15:0] channel_0,
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input [15:0] channel_1,
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input decimate,
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output m_axis_data_tvalid,
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output [31:0] m_axis_data_tdata);
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wire [31:0] s_axis_data_tdata;
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wire m_axis_data_tvalid_s;
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wire [31:0] m_axis_data_tdata_s;
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assign s_axis_data_tdata = {channel_1, channel_0};
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assign m_axis_data_tvalid = (decimate == 1'b1) ? m_axis_data_tvalid_s : s_axis_data_tvalid;
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assign m_axis_data_tdata = (decimate == 1'b1) ? {m_axis_data_tdata_s[30:16], 1'b0, m_axis_data_tdata_s[14:0], 1'b0} : {channel_1, channel_0};
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fir_decim decimator (
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.aclk(aclk),
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.s_axis_data_tvalid(s_axis_data_tvalid),
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.s_axis_data_tready(s_axis_data_tready),
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.s_axis_data_tdata(s_axis_data_tdata),
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.m_axis_data_tvalid(m_axis_data_tvalid_s),
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.m_axis_data_tdata(m_axis_data_tdata_s)
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);
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endmodule // util_fir_dec
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