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pluto_hdl_adi/library/util_axis_fifo
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Istvan Csomortani 5ac728392d util_axis_fifo: Refactoring 
Refactor the AXI4 stream FIFO implementation.

  - Define a single address generator which supports both single and double
clock mode. (synchronous and asynchronous)
  - Fix FIFO status bits (empty/full). NOTE: In asynchronous mode the
flags can have a several clock cycle delay in function of the upstream/downstream
clock ratio.
  - In synchronous none FIFO mode (ADDRESS_WIDTH==0), the module acts as
    an AXI4 stream pipeline.
 		2020-12-04 11:00:53 +02:00
..
Makefile util_axis_fifo: Refactoring 2020-12-04 11:00:53 +02:00
util_axis_fifo.v util_axis_fifo: Refactoring 2020-12-04 11:00:53 +02:00
util_axis_fifo_address_generator.v util_axis_fifo: Refactoring 2020-12-04 11:00:53 +02:00
util_axis_fifo_ip.tcl util_axis_fifo: Refactoring 2020-12-04 11:00:53 +02:00