216 lines
7.0 KiB
Verilog
216 lines
7.0 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module rx_tb;
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parameter VCD_FILE = "rx_tb.vcd";
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parameter NUM_LANES = 1;
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parameter NUM_LINKS = 1;
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parameter OCTETS_PER_FRAME = 8;
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parameter FRAMES_PER_MULTIFRAME = 32;
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`include "tb_base.v"
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integer phy_reset_counter = 'h00;
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integer align_counter = 'h00;
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reg phy_ready = 1'b0;
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reg aligned = 1'b0;
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wire en_align;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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phy_reset_counter <= 'h00;
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phy_ready <= 1'b0;
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end else begin
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if (phy_reset_counter == 'h40) begin
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phy_ready <= 1'b1;
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end else begin
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phy_reset_counter <= phy_reset_counter + 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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aligned <= 1'b0;
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align_counter <= 'h00;
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end else if (phy_ready == 1'b1) begin
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if (en_align == 1'b1) begin
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if (align_counter == 'h20) begin
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aligned <= 1'b1;
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end else begin
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align_counter <= align_counter + 1;
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end
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end
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end
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end
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localparam KCHAR_ILAS_START = {3'd0,5'd28};
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localparam KCHAR_LANE_ALIGN = {3'd3,5'd28};
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localparam KCHAR_ILAS_CONFIG = {3'd4,5'd28};
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localparam KCHAR_CGS = {3'd5,5'd28};
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localparam KCHAR_FRAME_ALIGN = {3'd7,5'd28};
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reg [31:0] data = KCHAR_CGS;
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reg [3:0] charisk = 4'b1111;
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reg [3:0] disperr = 4'b0000;
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reg [3:0] notintable = 4'b0000;
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wire [NUM_LINKS-1:0] sync;
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integer counter = 'h00;
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wire [31:0] counter2 = (counter - 'h10) * 4;
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always @(posedge clk) begin
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if ( &sync == 1'b0 ) begin
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counter <= 'h00;
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charisk <= 4'b1111;
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data <= {KCHAR_CGS,KCHAR_CGS,KCHAR_CGS,KCHAR_CGS};
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end else begin
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counter <= counter + 1;
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if (counter >= 'h8 && counter < 'h28) begin
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if (counter % 'h8 == 'h0) begin
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if (counter != 'h10) begin
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data <= {24'h00,KCHAR_ILAS_START};
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charisk <= 4'b0001;
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end else begin
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data <= {16'hffaa,KCHAR_ILAS_CONFIG,KCHAR_ILAS_START};
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charisk <= 4'b0011;
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end
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end else if (counter % 'h8 == 'h7) begin
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data <= {KCHAR_LANE_ALIGN,24'h00};
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charisk <= 4'b1000;
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end else begin
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data <= {32'h00};
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charisk <= 4'b0000;
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end
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end else if (counter > 'h10) begin
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data <= (counter2 + 'h2) << 24 |
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(counter2 + 'h1) << 16 |
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(counter2 + 'h0) << 8 |
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(counter2 - 'h1);
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charisk <= 4'b0000;
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end
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end
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end
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wire [NUM_LANES-1:0] cfg_lanes_disable;
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wire [NUM_LINKS-1:0] cfg_links_disable;
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wire [7:0] cfg_beats_per_multiframe;
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wire [7:0] cfg_octets_per_frame;
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wire [7:0] cfg_lmfc_offset;
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wire cfg_sysref_oneshot;
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wire cfg_sysref_disable;
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wire cfg_disable_scrambler;
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wire cfg_buffer_early_release;
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always @(posedge clk) begin
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if ($urandom % 400 == 0)
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disperr <= 4'b1111;
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else if ($urandom % 400 == 1)
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disperr <= 4'b0001;
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else if ($urandom % 400 == 2)
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disperr <= 4'b0011;
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else if ($urandom % 400 == 3)
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disperr <= 4'b0111;
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else
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disperr <= 4'b0000;
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end
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wire [NUM_LANES*32-1:0] status_err_statistics_cnt;
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jesd204_rx_static_config #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
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.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
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) i_cfg (
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.clk(clk),
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.cfg_lanes_disable(cfg_lanes_disable),
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.cfg_links_disable(cfg_links_disable),
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.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
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.cfg_octets_per_frame(cfg_octets_per_frame),
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.cfg_lmfc_offset(cfg_lmfc_offset),
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.cfg_sysref_oneshot(cfg_sysref_oneshot),
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.cfg_sysref_disable(cfg_sysref_disable),
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.cfg_disable_scrambler(cfg_disable_scrambler),
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.cfg_buffer_early_release(cfg_buffer_early_release)
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);
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jesd204_rx #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS)
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) i_rx (
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.clk(clk),
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.reset(reset),
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.cfg_lanes_disable(cfg_lanes_disable),
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.cfg_links_disable(cfg_links_disable),
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.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
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.cfg_octets_per_frame(cfg_octets_per_frame),
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.cfg_lmfc_offset(cfg_lmfc_offset),
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.cfg_sysref_oneshot(cfg_sysref_oneshot),
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.cfg_sysref_disable(cfg_sysref_disable),
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.cfg_disable_scrambler(cfg_disable_scrambler),
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.cfg_buffer_early_release(cfg_buffer_early_release),
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.ctrl_err_statistics_reset(1'b0),
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.ctrl_err_statistics_mask(3'h7),
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.status_err_statistics_cnt(status_err_statistics_cnt),
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.phy_en_char_align(en_align),
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.phy_data({NUM_LANES{data}}),
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.phy_charisk({NUM_LANES{charisk}}),
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.phy_notintable({NUM_LANES{notintable}}),
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.phy_disperr({NUM_LANES{disperr}}),
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.sync(sync),
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.sysref(sysref)
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);
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endmodule
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