315 lines
11 KiB
Verilog
315 lines
11 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_regmap_request #(
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parameter DISABLE_DEBUG_REGISTERS = 0,
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parameter BYTES_PER_BEAT_WIDTH_DEST = 1,
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parameter BYTES_PER_BEAT_WIDTH_SRC = 1,
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parameter BYTES_PER_BURST_WIDTH = 7,
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parameter DMA_AXI_ADDR_WIDTH = 32,
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parameter DMA_LENGTH_WIDTH = 24,
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parameter DMA_LENGTH_ALIGN = 3,
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parameter DMA_CYCLIC = 0,
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parameter HAS_DEST_ADDR = 1,
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parameter HAS_SRC_ADDR = 1,
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parameter DMA_2D_TRANSFER = 0,
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parameter SYNC_TRANSFER_START = 0
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) (
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input clk,
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input reset,
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// Interrupts
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output up_sot,
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output up_eot,
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// Register map interface
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input up_wreq,
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input up_rreq,
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input [8:0] up_waddr,
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input [31:0] up_wdata,
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input [8:0] up_raddr,
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output reg [31:0] up_rdata,
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// Control interface
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input ctrl_enable,
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// DMA request interface
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output request_valid,
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input request_ready,
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output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] request_dest_address,
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output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] request_src_address,
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output [DMA_LENGTH_WIDTH-1:0] request_x_length,
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output [DMA_LENGTH_WIDTH-1:0] request_y_length,
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output [DMA_LENGTH_WIDTH-1:0] request_dest_stride,
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output [DMA_LENGTH_WIDTH-1:0] request_src_stride,
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output request_sync_transfer_start,
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output request_last,
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// DMA response interface
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input response_eot,
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input [BYTES_PER_BURST_WIDTH-1:0] response_measured_burst_length,
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input response_partial,
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input response_valid,
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output reg response_ready = 1'b1
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);
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localparam MEASURED_LENGTH_WIDTH = (DMA_2D_TRANSFER == 1) ? 32 : DMA_LENGTH_WIDTH;
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// DMA transfer signals
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reg up_dma_req_valid = 1'b0;
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wire up_dma_req_ready;
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reg [1:0] up_transfer_id = 2'b0;
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reg [1:0] up_transfer_id_eot = 2'b0;
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reg [3:0] up_transfer_done_bitmap = 4'b0;
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reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00;
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reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00;
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reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = {DMA_LENGTH_ALIGN{1'b1}};
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reg up_dma_cyclic = DMA_CYCLIC ? 1'b1 : 1'b0;
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reg up_dma_last = 1'b1;
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reg up_dma_enable_tlen_reporting = 1'b0;
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wire up_tlf_s_ready;
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reg up_tlf_s_valid = 1'b0;
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wire [MEASURED_LENGTH_WIDTH+2-1:0] up_tlf_data;
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wire up_tlf_valid;
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wire up_tlf_rd;
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reg up_partial_length_valid = 1'b0;
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reg [MEASURED_LENGTH_WIDTH-1:0] up_measured_transfer_length = 'h0;
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reg up_clear_tl = 1'b0;
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reg [1:0] up_transfer_id_eot_d = 'h0;
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wire up_bl_partial;
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assign request_dest_address = up_dma_dest_address;
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assign request_src_address = up_dma_src_address;
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assign request_x_length = up_dma_x_length;
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assign request_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0;
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assign request_last = up_dma_last;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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up_dma_src_address <= 'h00;
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up_dma_dest_address <= 'h00;
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up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= 'h00;
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up_dma_req_valid <= 1'b0;
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up_dma_cyclic <= DMA_CYCLIC ? 1'b1 : 1'b0;
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up_dma_last <= 1'b1;
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up_dma_enable_tlen_reporting <= 1'b0;
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end else begin
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if (ctrl_enable == 1'b1) begin
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if (up_wreq == 1'b1 && up_waddr == 9'h102) begin
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up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
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end else if (up_sot == 1'b1) begin
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up_dma_req_valid <= 1'b0;
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end
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end else begin
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up_dma_req_valid <= 1'b0;
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end
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if (up_wreq == 1'b1) begin
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case (up_waddr)
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9'h103: begin
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if (DMA_CYCLIC) up_dma_cyclic <= up_wdata[0];
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up_dma_last <= up_wdata[1];
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up_dma_enable_tlen_reporting <= up_wdata[2];
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end
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9'h104: up_dma_dest_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
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9'h105: up_dma_src_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
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9'h106: up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= up_wdata[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN];
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endcase
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end
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end
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end
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always @(*) begin
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case (up_raddr)
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9'h101: up_rdata <= up_transfer_id;
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9'h102: up_rdata <= up_dma_req_valid;
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9'h103: up_rdata <= {29'h00, up_dma_enable_tlen_reporting, up_dma_last, up_dma_cyclic}; // Flags
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9'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
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9'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
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9'h106: up_rdata <= up_dma_x_length;
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9'h107: up_rdata <= request_y_length;
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9'h108: up_rdata <= request_dest_stride;
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9'h109: up_rdata <= request_src_stride;
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9'h10a: up_rdata <= {up_partial_length_valid,27'b0,up_transfer_done_bitmap};
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9'h10b: up_rdata <= up_transfer_id_eot;
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9'h10c: up_rdata <= 32'h0;
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9'h112: up_rdata <= up_measured_transfer_length;
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9'h113: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH-1 : 0]; // Length
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9'h114: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH+: 2]; // ID
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default: up_rdata <= 32'h00;
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endcase
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end
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generate
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if (DMA_2D_TRANSFER == 1) begin
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reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
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reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
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reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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up_dma_y_length <= 'h00;
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up_dma_dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] <= 'h00;
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up_dma_src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] <= 'h00;
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end else if (up_wreq == 1'b1) begin
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case (up_waddr)
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9'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
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9'h108: up_dma_dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] <= up_wdata[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
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9'h109: up_dma_src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] <= up_wdata[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
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endcase
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end
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end
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assign request_y_length = up_dma_y_length;
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assign request_dest_stride = up_dma_dest_stride;
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assign request_src_stride = up_dma_src_stride;
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end else begin
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assign request_y_length = 'h0;
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assign request_dest_stride = 'h0;
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assign request_src_stride = 'h0;
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end
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endgenerate
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// In cyclic mode the same transfer is submitted over and over again
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assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
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assign up_eot = up_dma_cyclic ? 1'b0 : response_eot & response_valid & response_ready;
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assign request_valid = up_dma_req_valid;
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assign up_dma_req_ready = request_ready;
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// Request ID and Request done bitmap handling
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always @(posedge clk) begin
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if (ctrl_enable == 1'b0) begin
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up_transfer_id <= 2'h0;
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up_transfer_id_eot <= 2'h0;
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up_transfer_done_bitmap <= 4'h0;
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end else begin
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if (up_sot == 1'b1) begin
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up_transfer_id <= up_transfer_id + 1'b1;
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up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
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end
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if (up_eot == 1'b1) begin
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up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
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up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
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end
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end
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end
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assign up_tlf_rd = up_rreq && up_raddr == 'h114;
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assign up_bl_partial = response_valid & response_ready & response_partial & up_dma_enable_tlen_reporting;
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always @(posedge clk) begin
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if (ctrl_enable == 1'b0) begin
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up_partial_length_valid <= 1'b0;
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end else begin
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if (up_bl_partial == 1'b1) begin
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up_partial_length_valid <= 1'b1;
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end else if (up_tlf_rd == 1'b1) begin
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up_partial_length_valid <= 1'b0;
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end else if (up_tlf_valid == 1'b1) begin
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up_partial_length_valid <= 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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if (ctrl_enable == 1'b0) begin
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up_measured_transfer_length <= 'h0;
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end else if (response_valid == 1'b1 && response_ready == 1'b1) begin
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up_measured_transfer_length <= up_measured_transfer_length + response_measured_burst_length + 1'b1;
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end else if (up_clear_tl == 1'b1) begin
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up_measured_transfer_length <= 'h0;
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end
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end
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always @(posedge clk) begin
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if (response_valid == 1'b1 && response_ready == 1'b1) begin
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up_transfer_id_eot_d <= up_transfer_id_eot;
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end
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end
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always @(posedge clk) begin
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if (ctrl_enable == 1'b0) begin
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response_ready <= 1'b1;
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end else if (response_ready == 1'b1) begin
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response_ready <= ~response_valid;
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end else if (up_tlf_s_ready == 1'b1) begin
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response_ready <= 1'b1;
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end
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end
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always @(posedge clk)
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begin
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if (response_valid == 1'b1 && response_ready == 1'b1) begin
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up_tlf_s_valid <= up_bl_partial;
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up_clear_tl <= response_eot;
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end else if (up_tlf_s_ready == 1'b1) begin
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up_tlf_s_valid <= 1'b0;
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end
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end
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// Buffer the length and transfer ID of partial transfers
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util_axis_fifo #(
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.DATA_WIDTH(MEASURED_LENGTH_WIDTH + 2),
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.ADDRESS_WIDTH(2),
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.ASYNC_CLK(0)
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) i_transfer_lenghts_fifo (
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.s_axis_aclk(clk),
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.s_axis_aresetn(ctrl_enable),
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.s_axis_valid(up_tlf_s_valid),
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.s_axis_ready(up_tlf_s_ready),
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.s_axis_full(),
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.s_axis_data({up_transfer_id_eot_d, up_measured_transfer_length}),
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.s_axis_room(),
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.m_axis_aclk(clk),
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.m_axis_aresetn(ctrl_enable),
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.m_axis_valid(up_tlf_valid),
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.m_axis_ready(up_tlf_rd & up_tlf_valid),
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.m_axis_data(up_tlf_data),
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.m_axis_level(),
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.m_axis_empty ()
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);
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endmodule
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