f730f14d16
Currently the ILAS memory for the receive register map uses a shift register with variable tap output for storing the ILAS information. This maps very efficiently onto the primitives found in Xilinx FPGAs. But there is no equivalent primitive in Altera FPAGs resulting in increased utilization from having to implement the structure in pure logic. Change the ILAS memory so it uses a simple dual port RAM for storing the data. This has slightly increased utilization on Xilinx platforms (but still good enough) and highly decreased utilization on Altera platforms. One side effect of this change is that since the RAM output is synchronous reading the ILAS memory registers will take one extra clock cycle. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| Makefile | ||
| axi_jesd204_rx.v | ||
| axi_jesd204_rx_constr.xdc | ||
| axi_jesd204_rx_ip.tcl | ||
| jesd204_up_ilas_mem.v | ||
| jesd204_up_rx.v | ||
| jesd204_up_rx_lane.v | ||