8dc2161870
In its default configuration the ram_2port module as a read latency of 2 clock cycles. Both the read address as well as the output data are registered. This is not the behavior that is expected from the alt_mem_asym module and causes incorrect behavior and data corruption in the util_adc_fifo. Disable the data output register to get a read latency of 1 clock cycle. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| avl_adxcfg | ||
| avl_adxcvr | ||
| avl_adxcvr_octet_swap | ||
| avl_adxphy | ||
| avl_dacfifo | ||
| axi_adxcvr | ||
| common | ||