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pluto_hdl_adi/library/altera/avl_dacfifo
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Istvan Csomortani e3ea51ade3 avl_dacfifo: Refactor the fifo 
+ Build both the read and write logic around an FSM
 + Consistent naming of registers and wires
 + Add support for burst lenghts higher than one, current burst lenght
is 64
 + Fix all the bugs, and make it work (first bring up with
adrv9371x/a10soc)
 		2017-10-31 14:30:06 +00:00
..
avl_dacfifo.v avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00
avl_dacfifo_byteenable_coder.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
avl_dacfifo_byteenable_decoder.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
avl_dacfifo_constr.sdc avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00
avl_dacfifo_hw.tcl avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00
avl_dacfifo_rd.v avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00
avl_dacfifo_wr.v avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00
util_dacfifo_bypass.v avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00