323 lines
10 KiB
Verilog
323 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_xcvrlb_1 (
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// transceiver interface
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input ref_clk,
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input rx_p,
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input rx_n,
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output tx_p,
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output tx_n,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_resetn,
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output up_status);
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// internal registers
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reg [ 3:0] rx_kcount = 'd0;
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reg rx_calign = 'd0;
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reg [31:0] rx_data = 'd0;
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reg [31:0] rx_pn_data = 'd0;
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reg tx_charisk = 'd0;
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reg [31:0] tx_data = 'd0;
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reg [31:0] tx_pn_data = 'd0;
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reg [ 3:0] up_pll_rst_cnt = 'd0;
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reg [ 3:0] up_rst_cnt = 'd0;
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reg [ 6:0] up_user_ready_cnt = 'd0;
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reg up_status_int = 'd1;
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// internal signals
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wire clk;
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wire rx_status_s;
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wire [31:0] rx_pn_data_s;
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wire rx_pn_oos_s;
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wire rx_pn_err_s;
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wire [ 3:0] rx_charisk_s;
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wire [ 7:0] rx_error_s;
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wire [31:0] rx_data_s;
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wire up_pll_rst_s;
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wire up_rst_s;
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wire up_user_ready_s;
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wire up_pll_locked_s;
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wire up_rst_done_s;
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wire up_pn_oos_s;
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wire up_pn_err_s;
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wire up_rx_pll_locked_s;
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wire up_rx_rst_done_s;
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wire up_tx_pll_locked_s;
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wire up_tx_rst_done_s;
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// pn31 function
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function [31:0] pn31;
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input [31:0] din;
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reg [31:0] dout;
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begin
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dout[31] = din[31] ^ din[28];
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dout[30] = din[30] ^ din[27];
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dout[29] = din[29] ^ din[26];
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dout[28] = din[28] ^ din[25];
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dout[27] = din[27] ^ din[24];
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dout[26] = din[26] ^ din[23];
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dout[25] = din[25] ^ din[22];
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dout[24] = din[24] ^ din[21];
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dout[23] = din[23] ^ din[20];
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dout[22] = din[22] ^ din[19];
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dout[21] = din[21] ^ din[18];
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dout[20] = din[20] ^ din[17];
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dout[19] = din[19] ^ din[16];
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dout[18] = din[18] ^ din[15];
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dout[17] = din[17] ^ din[14];
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dout[16] = din[16] ^ din[13];
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dout[15] = din[15] ^ din[12];
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dout[14] = din[14] ^ din[11];
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dout[13] = din[13] ^ din[10];
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dout[12] = din[12] ^ din[ 9];
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dout[11] = din[11] ^ din[ 8];
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dout[10] = din[10] ^ din[ 7];
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dout[ 9] = din[ 9] ^ din[ 6];
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dout[ 8] = din[ 8] ^ din[ 5];
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dout[ 7] = din[ 7] ^ din[ 4];
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dout[ 6] = din[ 6] ^ din[ 3];
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dout[ 5] = din[ 5] ^ din[ 2];
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dout[ 4] = din[ 4] ^ din[ 1];
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dout[ 3] = din[ 3] ^ din[ 0];
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dout[ 2] = din[ 2] ^ din[31] ^ din[28];
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dout[ 1] = din[ 1] ^ din[30] ^ din[27];
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dout[ 0] = din[ 0] ^ din[29] ^ din[26];
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pn31 = dout;
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end
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endfunction
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// receive
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assign rx_status_s = ~(| rx_error_s);
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assign rx_pn_data_s = (rx_pn_oos_s == 1'b1) ? rx_data : rx_pn_data;
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always @(posedge clk) begin
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if (rx_status_s == 1'b0) begin
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rx_kcount <= 4'd0;
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rx_calign <= 1'd1;
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end else if ((rx_charisk_s == 4'hf) && (rx_data_s == {4{8'hbc}})) begin
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rx_kcount <= rx_kcount + 1'b1;
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if (rx_kcount == 4'hf) begin
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rx_calign <= 1'd0;
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end
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end
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end
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always @(posedge clk) begin
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if (rx_status_s == 1'b1) begin
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rx_data[31:24] = rx_data_s[ 7: 0];
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rx_data[23:16] = rx_data_s[15: 8];
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rx_data[15: 8] = rx_data_s[23:16];
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rx_data[ 7: 0] = rx_data_s[31:24];
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end else begin
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rx_data[31:24] = 8'hff;
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rx_data[23:16] = 8'hff;
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rx_data[15: 8] = 8'hff;
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rx_data[ 7: 0] = 8'hff;
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end
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rx_pn_data <= pn31(rx_pn_data_s);
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end
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// transmit
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always @(posedge clk) begin
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if (rx_calign == 1'b0) begin
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tx_charisk <= 1'd0;
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tx_data[31:24] <= tx_pn_data[ 7: 0];
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tx_data[23:16] <= tx_pn_data[15: 8];
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tx_data[15: 8] <= tx_pn_data[23:16];
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tx_data[ 7: 0] <= tx_pn_data[31:24];
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tx_pn_data <= pn31(tx_pn_data);
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end else begin
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tx_charisk <= 1'd1;
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tx_data[31:24] <= 8'hbc;
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tx_data[23:16] <= 8'hbc;
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tx_data[15: 8] <= 8'hbc;
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tx_data[ 7: 0] <= 8'hbc;
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tx_pn_data <= {32{1'b1}};
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end
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end
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// reset & init
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assign up_status = up_status_int;
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assign up_pll_rst_s = up_pll_rst_cnt[3];
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assign up_rst_s = up_rst_cnt[3];
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assign up_user_ready_s = up_user_ready_cnt[6];
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assign up_pll_locked_s = up_rx_pll_locked_s & up_tx_pll_locked_s;
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assign up_rst_done_s = up_rx_rst_done_s & up_tx_rst_done_s;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_pll_rst_cnt <= 4'h8;
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up_rst_cnt <= 4'h8;
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up_user_ready_cnt <= 7'h00;
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up_status_int <= 1'b1;
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end else begin
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if (up_resetn == 1'b0) begin
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up_pll_rst_cnt <= 4'h8;
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end else if (up_pll_rst_cnt[3] == 1'b1) begin
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up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1;
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end
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if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) ||
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(up_pll_locked_s == 1'b0)) begin
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up_rst_cnt <= 4'h8;
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end else if (up_rst_cnt[3] == 1'b1) begin
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up_rst_cnt <= up_rst_cnt + 1'b1;
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end
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if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin
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up_user_ready_cnt <= 7'h00;
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end else if (up_user_ready_cnt[6] == 1'b0) begin
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up_user_ready_cnt <= up_user_ready_cnt + 1'b1;
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end
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if ((up_resetn == 1'b0) || (up_rst_done_s == 1'b0)) begin
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up_status_int <= 1'b1;
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end else begin
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up_status_int <= up_pn_oos_s | up_pn_err_s;
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end
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end
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end
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// instantiations
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ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
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.adc_clk (clk),
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.adc_valid_in (1'b1),
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.adc_data_in (rx_data),
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.adc_data_pn (rx_pn_data),
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.adc_pn_oos (rx_pn_oos_s),
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.adc_pn_err (rx_pn_err_s));
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up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_status ({up_pn_err_s, up_pn_oos_s}),
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.d_rst (1'b0),
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.d_clk (clk),
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.d_data_status ({rx_pn_err_s, rx_pn_oos_s}));
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util_adxcvr_xch #(
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.XCVR_ID (0),
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.XCVR_TYPE (0),
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.CPLL_FBDIV (2),
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.CPLL_FBDIV_4_5 (5),
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.TX_OUT_DIV (1),
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.TX_CLK25_DIV (10),
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.RX_OUT_DIV (1),
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.RX_CLK25_DIV (10),
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.RX_DFE_LPM_CFG (16'h0904),
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.RX_PMA_CFG ('h00018480),
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.RX_CDR_CFG ('h03000023ff10200020))
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i_xch (
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.qpll2ch_clk (1'b0),
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.qpll2ch_ref_clk (1'b0),
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.qpll2ch_locked (1'b1),
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.cpll_ref_clk (ref_clk),
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.up_cpll_rst (up_pll_rst_s),
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.rx_p (rx_p),
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.rx_n (rx_n),
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.rx_out_clk (clk),
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.rx_clk (clk),
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.rx_charisk (rx_charisk_s),
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.rx_disperr (rx_error_s[3:0]),
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.rx_notintable (rx_error_s[7:4]),
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.rx_data (rx_data_s),
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.rx_calign (rx_calign),
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.tx_p (tx_p),
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.tx_n (tx_n),
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.tx_out_clk (),
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.tx_clk (clk),
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.tx_charisk ({4{tx_charisk}}),
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.tx_data (tx_data),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_es_sel (1'd0),
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.up_es_enb (1'd0),
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.up_es_addr (12'd0),
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.up_es_wr (1'd0),
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.up_es_wdata (16'd0),
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.up_es_rdata (),
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.up_es_ready (),
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.up_rx_pll_locked (up_rx_pll_locked_s),
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.up_rx_rst (up_rst_s),
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.up_rx_user_ready (up_user_ready_s),
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.up_rx_rst_done (up_rx_rst_done_s),
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.up_rx_lpm_dfe_n (1'd0),
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.up_rx_rate (3'd0),
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.up_rx_sys_clk_sel (2'd0),
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.up_rx_out_clk_sel (3'd2),
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.up_rx_sel (1'd0),
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.up_rx_enb (1'd0),
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.up_rx_addr (12'd0),
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.up_rx_wr (1'd0),
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.up_rx_wdata (16'd0),
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.up_rx_rdata (),
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.up_rx_ready (),
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.up_tx_pll_locked (up_tx_pll_locked_s),
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.up_tx_rst (up_rst_s),
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.up_tx_user_ready (up_user_ready_s),
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.up_tx_rst_done (up_tx_rst_done_s),
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.up_tx_lpm_dfe_n (1'd0),
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.up_tx_rate (3'd0),
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.up_tx_sys_clk_sel (2'd0),
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.up_tx_out_clk_sel (3'd2),
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.up_tx_sel (1'd0),
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.up_tx_enb (1'd0),
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.up_tx_addr (12'd0),
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.up_tx_wr (1'd0),
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.up_tx_wdata (16'd0),
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.up_tx_rdata (),
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.up_tx_ready ());
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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