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Adrian Costina f5de5ca487 usdrx1: Fixed jesd core parameters. Fixed synchronization mechanism 2015-08-19 10:12:24 +03:00
library usdrx1: Fixed jesd core parameters. Fixed synchronization mechanism 2015-08-19 10:12:24 +03:00
projects usdrx1: Fixed jesd core parameters. Fixed synchronization mechanism 2015-08-19 10:12:24 +03:00
.gitattributes Add .gitattributes file 2015-07-01 18:43:51 +02:00
.gitignore gitignore: add non-project stuff 2015-05-01 13:17:14 -04:00
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Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update to Quartus 15.0. Removed release candidate note 2015-08-13 11:55:23 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

###Tools version:

###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

For support please visit our FPGA Reference Designs Support Community on EngineerZone.