Istvan Csomortani 61ece1f1e9 s10soc: Insert an additional bridge between DMA and HPS ... Due to the interface differences between HPS's AXI4 and DMA's AXI4, the tool will try to automaticaly add some bridges between the two interface. Unfortunatly it does generate timing issues at the f2sdram0 interface of the HPS instance. By explicitly instantiating an AXI bridge, these timing issues disappears.		2020-09-09 14:15:37 +03:00
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s10soc_system_assign.tcl	stratix10soc: Initial commit of base design	2020-09-09 14:15:37 +03:00
s10soc_system_qsys.tcl	s10soc: Insert an additional bridge between DMA and HPS	2020-09-09 14:15:37 +03:00