f51c941c2d
Instead of just marking all clock domains as asynchronous set the appropriate constraints for each CDC path. For single-bit synchronizers use set_false_path to not constraint the path at at all. For multi-bit synchronizers as used for gray counters use set_max_delay with the source clock period domain to make sure that the signal skew will not exceed one clock period. Otherwise one bit might overtake another and the synchronizer no longer works correctly. For multi-bit synchronizers implemented with hold registers use set_max_delay with the target clock period to make sure that the skew does not get to large, otherwise we might violate setup and hold time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
hdl
Analog Devices HDL libraries and projects
Tools version:
- Vivado 2014.4.1
- Quartus 14.0
First time users, it is highly recommended to go through our HDL user guide at the following url:
http://wiki.analog.com/resources/fpga/docs/hdl
For support please visit our FPGA Reference Designs Support Community on EngineerZone: