503 lines
18 KiB
Verilog
503 lines
18 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module avl_dacfifo_wr #(
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parameter AVL_DATA_WIDTH = 512,
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parameter DMA_DATA_WIDTH = 64,
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parameter AVL_DDR_BASE_ADDRESS = 0,
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parameter AVL_DDR_ADDRESS_LIMIT = 1048576,
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parameter DMA_MEM_ADDRESS_WIDTH = 8)(
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input dma_clk,
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input [DMA_DATA_WIDTH-1:0] dma_data,
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input dma_ready,
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output reg dma_ready_out,
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input dma_valid,
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input dma_xfer_req,
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input dma_xfer_last,
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output reg [ 3:0] dma_last_beat,
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input avl_clk,
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input avl_reset,
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output reg [24:0] avl_address,
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output [ 5:0] avl_burstcount,
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output reg [63:0] avl_byteenable,
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input avl_ready,
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output reg avl_write,
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output reg [AVL_DATA_WIDTH-1:0] avl_data,
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output reg [24:0] avl_last_address,
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output reg [63:0] avl_last_byteenable,
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output reg avl_xfer_req);
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localparam MEM_RATIO = AVL_DATA_WIDTH/DMA_DATA_WIDTH; // Max supported MEM_RATIO is 16
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localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH :
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(MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) :
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(MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) :
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(MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) :
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(DMA_MEM_ADDRESS_WIDTH - 4);
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localparam MEM_WIDTH_DIFF = (MEM_RATIO > 8) ? 4 :
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(MEM_RATIO > 4) ? 3 :
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(MEM_RATIO > 2) ? 2 :
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(MEM_RATIO > 1) ? 1 : 1;
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localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - 4;
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localparam DMA_BYTE_DATA_WIDTH = DMA_DATA_WIDTH/8;
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localparam AVL_BYTE_DATA_WIDTH = AVL_DATA_WIDTH/8;
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wire dma_resetn;
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wire dma_mem_wea_s;
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wire [DMA_MEM_ADDRESS_WIDTH :0] dma_mem_address_diff_s;
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wire [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_rd_address_s;
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wire [AVL_DATA_WIDTH-1:0] avl_mem_rdata_s;
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wire avl_mem_fetch_wr_address_s;
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wire avl_mem_readen_s;
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wire avl_write_transfer_s;
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wire avl_last_transfer_req_s;
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wire avl_xfer_req_init_s;
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wire avl_write_transfer_done_s;
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reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_wr_address;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_wr_address_d;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_rd_address_m1;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_rd_address_m2;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_rd_address;
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reg dma_mem_read_control;
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reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_address_diff;
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reg dma_last_beat_ack;
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reg [MEM_WIDTH_DIFF-1:0] dma_mem_last_beats;
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reg dma_avl_xfer_req_m1;
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reg dma_avl_xfer_req;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_g;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address_next;
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reg avl_mem_fetch_wr_address;
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reg avl_mem_fetch_wr_address_m1;
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reg avl_mem_fetch_wr_address_m2;
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reg avl_write_d;
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reg avl_mem_readen;
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reg avl_write_transfer;
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reg avl_last_beat_req_m1;
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reg avl_last_beat_req_m2;
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reg avl_last_beat_req;
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reg avl_dma_xfer_req;
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reg avl_dma_xfer_req_m1;
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reg avl_dma_xfer_req_m2;
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reg [MEM_WIDTH_DIFF-1:0] avl_last_beats;
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reg [MEM_WIDTH_DIFF-1:0] avl_last_beats_m1;
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reg [MEM_WIDTH_DIFF-1:0] avl_last_beats_m2;
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reg avl_write_xfer_req;
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reg avl_write_xfer_req_d;
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// binary to grey conversion
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function [7:0] b2g;
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input [7:0] b;
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reg [7:0] g;
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begin
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g[7] = b[7];
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g[6] = b[7] ^ b[6];
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g[5] = b[6] ^ b[5];
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g[4] = b[5] ^ b[4];
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g[3] = b[4] ^ b[3];
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g[2] = b[3] ^ b[2];
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g[1] = b[2] ^ b[1];
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g[0] = b[1] ^ b[0];
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b2g = g;
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end
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endfunction
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// grey to binary conversion
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function [7:0] g2b;
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input [7:0] g;
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reg [7:0] b;
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begin
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b[7] = g[7];
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b[6] = b[7] ^ g[6];
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b[5] = b[6] ^ g[5];
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b[4] = b[5] ^ g[4];
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b[3] = b[4] ^ g[3];
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b[2] = b[3] ^ g[2];
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b[1] = b[2] ^ g[1];
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b[0] = b[1] ^ g[0];
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g2b = b;
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end
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endfunction
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// An asymmetric memory to transfer data from DMAC interface to AXI Memory Map
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// interface
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ad_mem_asym #(
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.A_ADDRESS_WIDTH (DMA_MEM_ADDRESS_WIDTH),
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.A_DATA_WIDTH (DMA_DATA_WIDTH),
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.B_ADDRESS_WIDTH (AVL_MEM_ADDRESS_WIDTH),
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.B_DATA_WIDTH (AVL_DATA_WIDTH))
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i_mem_asym (
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.clka (dma_clk),
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.wea (dma_mem_wea_s),
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.addra (dma_mem_wr_address),
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.dina (dma_data),
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.clkb (avl_clk),
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.addrb (avl_mem_rd_address),
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.doutb (avl_mem_rdata_s));
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// the fifo reset is the dma_xfer_req
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assign dma_resetn = dma_xfer_req;
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// write address generation
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assign dma_mem_address_diff_s = {1'b1, dma_mem_wr_address} - dma_mem_rd_address_s;
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assign dma_mem_rd_address_s = (MEM_RATIO == 1) ? dma_mem_rd_address :
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(MEM_RATIO == 2) ? {dma_mem_rd_address, 1'b0} :
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(MEM_RATIO == 4) ? {dma_mem_rd_address, 2'b0} :
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(MEM_RATIO == 8) ? {dma_mem_rd_address, 3'b0} :
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{dma_mem_rd_address, 4'b0};
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assign dma_mem_wea_s = dma_ready & dma_valid & dma_xfer_req;
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always @(posedge dma_clk) begin
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if (dma_resetn == 1'b0) begin
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dma_mem_wr_address <= 0;
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dma_mem_read_control <= 1'b0;
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dma_mem_last_beats <= 0;
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end else begin
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if (dma_mem_wea_s == 1'b1) begin
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dma_mem_wr_address <= dma_mem_wr_address + 1;
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end
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if (dma_mem_wr_address[MEM_WIDTH_DIFF-1:0] == {MEM_WIDTH_DIFF{1'b1}}) begin
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dma_mem_read_control <= ~dma_mem_read_control;
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dma_mem_wr_address_d <= dma_mem_wr_address[DMA_MEM_ADDRESS_WIDTH-1:MEM_WIDTH_DIFF];
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end
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end
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if ((dma_xfer_last == 1'b1) && (dma_mem_wea_s)) begin
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dma_mem_last_beats <= dma_mem_wr_address[MEM_WIDTH_DIFF-1:0];
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end
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end
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// The memory module request data until reaches the high threshold.
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always @(posedge dma_clk) begin
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if (dma_resetn == 1'b0) begin
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dma_mem_address_diff <= 'b0;
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dma_mem_rd_address_m1 <= 'b0;
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dma_mem_rd_address_m2 <= 'b0;
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dma_mem_rd_address <= 'b0;
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dma_ready_out <= 1'b0;
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end else begin
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dma_mem_rd_address_m1 <= avl_mem_rd_address_g;
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dma_mem_rd_address_m2 <= dma_mem_rd_address_m1;
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dma_mem_rd_address <= g2b(dma_mem_rd_address_m2);
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dma_mem_address_diff <= dma_mem_address_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0];
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if (dma_mem_address_diff >= DMA_BUF_THRESHOLD_HI) begin
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dma_ready_out <= 1'b0;
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end else begin
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dma_ready_out <= 1'b1;
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end
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end
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end
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// last DMA beat
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always @(posedge dma_clk) begin
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dma_avl_xfer_req_m1 <= avl_write_xfer_req;
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dma_avl_xfer_req <= dma_avl_xfer_req_m1;
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end
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always @(posedge dma_clk) begin
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if (dma_avl_xfer_req == 1'b0) begin
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dma_last_beat_ack <= 1'b0;
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end else begin
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if ((dma_xfer_req == 1'b1) && (dma_xfer_last == 1'b1)) begin
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dma_last_beat_ack <= 1'b1;
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end
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end
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end
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// transfer the mem_write address to the avalons clock domain
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assign avl_mem_fetch_wr_address_s = avl_mem_fetch_wr_address ^ avl_mem_fetch_wr_address_m1;
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always @(posedge avl_clk) begin
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if (avl_reset == 1'b1) begin
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avl_mem_fetch_wr_address_m1 <= 0;
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avl_mem_fetch_wr_address_m2 <= 0;
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avl_mem_fetch_wr_address <= 0;
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avl_mem_wr_address <= 0;
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avl_mem_wr_address_next <= 0;
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end else begin
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avl_mem_fetch_wr_address_m1 <= dma_mem_read_control;
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avl_mem_fetch_wr_address_m2 <= avl_mem_fetch_wr_address_m1;
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avl_mem_fetch_wr_address <= avl_mem_fetch_wr_address_m2;
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if (avl_mem_fetch_wr_address_s == 1'b1) begin
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avl_mem_wr_address <= dma_mem_wr_address_d;
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avl_mem_wr_address_next <= avl_mem_wr_address + 1;
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end
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end
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end
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// Avalon write address and fifo read address generation
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assign avl_mem_readen_s = (avl_mem_rd_address == avl_mem_wr_address_next) ? 0 : avl_write_xfer_req;
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assign avl_write_transfer_s = avl_write & avl_ready;
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assign avl_write_transfer_done_s = avl_write_transfer & ~avl_write_transfer_s;
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always @(posedge avl_clk) begin
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if ((avl_reset == 1'b1) || (avl_write_xfer_req == 1'b0)) begin
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avl_address <= AVL_DDR_BASE_ADDRESS;
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avl_data <= 0;
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avl_write_transfer <= 1'b0;
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avl_mem_readen <= 0;
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avl_mem_rd_address <= 0;
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avl_mem_rd_address_g <= 0;
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end else begin
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if (avl_write_transfer_done_s == 1'b1) begin
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avl_address <= (avl_address < AVL_DDR_ADDRESS_LIMIT) ? avl_address + 1 : 0;
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end
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if (avl_write_transfer_s == 1'b1) begin
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avl_mem_rd_address <= avl_mem_rd_address + 1;
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end
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avl_data <= avl_mem_rdata_s;
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avl_mem_rd_address_g <= b2g(avl_mem_rd_address);
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avl_write_transfer <= avl_write_transfer_s;
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avl_mem_readen <= avl_mem_readen_s;
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end
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end
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// avalon write signaling
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assign avl_last_transfer_req_s = avl_last_beat_req & ~avl_mem_readen;
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always @(negedge avl_clk) begin
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if (avl_reset == 1'b1) begin
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avl_write <= 1'b0;
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avl_write_d <= 1'b0;
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end else begin
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if ((((avl_mem_readen == 1'b1) && (avl_write_xfer_req == 1'b1)) ||
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((avl_last_transfer_req_s == 1'b1) && (avl_write_xfer_req == 1'b1))) &&
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(avl_write == 1'b0) && (avl_write_d == 1'b0)) begin
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avl_write <= 1'b1;
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end else if (avl_write_transfer == 1'b1) begin
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avl_write <= 1'b0;
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end
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avl_write_d <= avl_write;
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end
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end
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assign avl_xfer_req_init_s = ~avl_dma_xfer_req & avl_dma_xfer_req_m2;
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always @(posedge avl_clk) begin
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if (avl_reset == 1'b1) begin
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avl_last_beat_req_m1 <= 1'b0;
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avl_last_beat_req_m2 <= 1'b0;
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avl_last_beat_req <= 1'b0;
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avl_write_xfer_req <= 1'b0;
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avl_write_xfer_req_d <= 1'b0;
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avl_dma_xfer_req_m1 <= 1'b0;
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avl_dma_xfer_req_m2 <= 1'b0;
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avl_dma_xfer_req <= 1'b0;
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end else begin
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avl_last_beat_req_m1 <= dma_last_beat_ack;
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avl_last_beat_req_m2 <= avl_last_beat_req_m1;
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avl_last_beat_req <= avl_last_beat_req_m2;
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avl_dma_xfer_req_m1 <= dma_xfer_req;
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avl_dma_xfer_req_m2 <= avl_dma_xfer_req_m1;
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avl_dma_xfer_req <= avl_dma_xfer_req_m2;
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if (avl_xfer_req_init_s == 1'b1) begin
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avl_write_xfer_req <= 1'b1;
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end else if ((avl_last_transfer_req_s == 1'b1) &&
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(avl_write_transfer == 1'b1)) begin
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avl_write_xfer_req <= 1'b0;
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end
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avl_write_xfer_req_d <= avl_write_xfer_req;
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end
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end
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// generate avl_byteenable signal
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always @(posedge avl_clk) begin
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if (avl_reset == 1'b1) begin
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avl_last_beats_m1 <= 1'b0;
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avl_last_beats_m2 <= 1'b0;
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avl_last_beats <= 1'b0;
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end else begin
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avl_last_beats_m1 <= dma_mem_last_beats;
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avl_last_beats_m2 <= avl_last_beats_m1;
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avl_last_beats <= (avl_last_beat_req == 1'b1) ? avl_last_beats_m2 : avl_last_beats;
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end
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end
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always @(posedge avl_clk) begin
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if (avl_last_transfer_req_s == 1'b1) begin
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case (avl_last_beats)
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0 : begin
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case (MEM_RATIO)
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2 : avl_byteenable <= {32'b0, {32{1'b1}}};
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4 : avl_byteenable <= {48'b0, {16{1'b1}}};
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8 : avl_byteenable <= {56'b0, {8{1'b1}}};
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16 : avl_byteenable <= {60'b0, {4{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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1 : begin
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case (MEM_RATIO)
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4 : avl_byteenable <= {32'b0, {32{1'b1}}};
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8 : avl_byteenable <= {48'b0, {16{1'b1}}};
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16 : avl_byteenable <= {56'b0, {8{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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2 : begin
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case (MEM_RATIO)
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4 : avl_byteenable <= {16'b0, {48{1'b1}}};
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8 : avl_byteenable <= {40'b0, {24{1'b1}}};
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16 : avl_byteenable <= {52'b0, {12{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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3 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {32'b0, {32{1'b1}}};
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16 : avl_byteenable <= {48'b0, {16{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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4 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {24'b0, {40{1'b1}}};
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16 : avl_byteenable <= {44'b0, {20{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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5 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {16'b0, {48{1'b1}}};
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16 : avl_byteenable <= {40'b0, {24{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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6 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {8'b0, {56{1'b1}}};
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16 : avl_byteenable <= {36'b0, {28{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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7 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {32'b0, {32{1'b1}}};
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|
default : avl_byteenable <= {64{1'b1}};
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|
endcase
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|
end
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|
8 : begin
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case (MEM_RATIO)
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|
16 : avl_byteenable <= {28'b0, {36{1'b1}}};
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|
default : avl_byteenable <= {64{1'b1}};
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|
endcase
|
|
end
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|
9 : begin
|
|
case (MEM_RATIO)
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|
16 : avl_byteenable <= {24'b0, {40{1'b1}}};
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|
default : avl_byteenable <= {64{1'b1}};
|
|
endcase
|
|
end
|
|
10 : begin
|
|
case (MEM_RATIO)
|
|
16 : avl_byteenable <= {20'b0, {44{1'b1}}};
|
|
default : avl_byteenable <= {64{1'b1}};
|
|
endcase
|
|
end
|
|
11 : begin
|
|
case (MEM_RATIO)
|
|
16 : avl_byteenable <= {16'b0, {48{1'b1}}};
|
|
default : avl_byteenable <= {64{1'b1}};
|
|
endcase
|
|
end
|
|
12 : begin
|
|
case (MEM_RATIO)
|
|
16 : avl_byteenable <= {12'b0, {52{1'b1}}};
|
|
default : avl_byteenable <= {64{1'b1}};
|
|
endcase
|
|
end
|
|
13 : begin
|
|
case (MEM_RATIO)
|
|
16 : avl_byteenable <= {8'b0, {56{1'b1}}};
|
|
default : avl_byteenable <= {64{1'b1}};
|
|
endcase
|
|
end
|
|
14 : begin
|
|
case (MEM_RATIO)
|
|
16 : avl_byteenable <= {4'b0, {60{1'b1}}};
|
|
default : avl_byteenable <= {64{1'b1}};
|
|
endcase
|
|
end
|
|
15 : begin
|
|
avl_byteenable <= {64{1'b1}};
|
|
end
|
|
default : avl_byteenable <= {64{1'b1}};
|
|
endcase
|
|
end else begin
|
|
avl_byteenable <= {64{1'b1}};
|
|
end
|
|
end
|
|
|
|
assign avl_burstcount = 6'b1;
|
|
|
|
// save the last address and byteenable
|
|
|
|
always @(posedge avl_clk) begin
|
|
if (avl_reset == 1'b1) begin
|
|
avl_last_address <= 0;
|
|
avl_last_byteenable <= 0;
|
|
end else begin
|
|
if ((avl_write == 1'b1) && (avl_last_transfer_req_s == 1'b1)) begin
|
|
avl_last_address <= avl_address;
|
|
avl_last_byteenable <= avl_byteenable;
|
|
end
|
|
end
|
|
end
|
|
|
|
// avl_xfer_req generation for synchronize the access of the external
|
|
// memory
|
|
|
|
always @(posedge avl_clk) begin
|
|
if (avl_reset == 1'b1) begin
|
|
avl_xfer_req <= 1'b0;
|
|
end else begin
|
|
if ((avl_last_transfer_req_s == 1'b1) &&
|
|
(avl_write_transfer == 1'b1)) begin
|
|
avl_xfer_req <= 1'b1;
|
|
end else if ((avl_xfer_req == 1'b1) && (avl_dma_xfer_req == 1'b1)) begin
|
|
avl_xfer_req <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
endmodule
|