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Ionut Podgoreanu f41391fa93 axi_dmac: Add support for DMA Scatter-Gather 
This commit introduces a different interface to submit transfers, using
DMA descriptors.

The structure of the DMA descriptor is as follows:

struct dma_desc {
    u32 flags,
    u32 id,
    u64 dest_addr,
    u64 src_addr,
    u64 next_sg_addr,
    u32 y_len,
    u32 x_len,
    u32 src_stride,
    u32 dst_stride,
};

The 'flags' field currently offers two control bits:
- bit 0: if set, the transfer will complete after this last descriptor
  is processed, and the DMA core will go back to idle state; if cleared,
  the next DMA descriptor pointed to by 'next_sg_addr' will be loaded.
- bit 1: if set, an end-of-transfer interrupt will be raised after the
  memory segment pointed to by this descriptor has been transferred.

The 'id' field corresponds to an identifier of the descriptor.

The 'dest_addr' and 'src_addr' contain the destination and source
addresses to use for the transfer, respectively.

The 'x_len' field contains the number of bytes to transfer,
minus one.

The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for
2D transfers, and should be set to zero if 2D transfers are not
required.

To start a transfer, the address of the first DMA descriptor must be
written to register 0x47c and the HWDESC bit of CONTROL register must
be set. The Scatter-Gather transfer is queued similarly to the simple
transfers, by writing 1 in TRANSFER_SUBMIT.

The Scatter-Gather interface has a dedicated AXI-MM bus configured for
read transfers, with its own dedicated clock, which can be asynchronous.

The Scatter-Gather reset is generated by the reset manager to reset the
logic after completing any pending transactions on the bus.

When the Scatter-Gather is enabled during runtime, the legacy cyclic
functionality of the DMA is disabled.

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
 		2023-12-04 14:34:33 +02:00
..
ad463x_data_capture Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ad777x Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ad3552r library/axi_ad3552r: Added interface IP for Xilinx projects. 2023-10-02 11:07:08 +03:00
axi_ad4858 axi_ad4858: Initial commit 2023-10-05 10:19:03 +03:00
axi_ad5766 library/common: Added DAC custom read/write interface in up_dac_common. 2023-10-02 11:07:08 +03:00
axi_ad7606x axi_ad7606x: Add the correct IP's name 2023-11-07 15:00:06 +02:00
axi_ad7616 axi_ad7616: Remove serial dependencies 2023-11-09 14:43:20 +02:00
axi_ad7768 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ad9122 library/common: Added DAC custom read/write interface in up_dac_common. 2023-10-02 11:07:08 +03:00
axi_ad9250 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ad9265 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ad9361 library/common: Added DAC custom read/write interface in up_dac_common. 2023-10-02 11:07:08 +03:00
axi_ad9434 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ad9467 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ad9625 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ad9671 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ad9684 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ad9739a library/common: Added DAC custom read/write interface in up_dac_common. 2023-10-02 11:07:08 +03:00
axi_ad9783 library/common: Added DAC custom read/write interface in up_dac_common. 2023-10-02 11:07:08 +03:00
axi_ad9963 library/common: Added DAC custom read/write interface in up_dac_common. 2023-10-02 11:07:08 +03:00
axi_adaq8092 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_adc_decimate Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_adc_trigger Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_adrv9001 library/common: Added DAC custom read/write interface in up_dac_common. 2023-10-02 11:07:08 +03:00
axi_clkgen Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_clock_monitor Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_dac_interpolate Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_dmac axi_dmac: Add support for DMA Scatter-Gather 2023-12-04 14:34:33 +02:00
axi_fan_control Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_fmcadc5_sync Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_generic_adc Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_gpreg Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_hdmi_rx Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_hdmi_tx Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_i2s_adi Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_intr_monitor Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_laser_driver Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_logic_analyzer Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_ltc235x dc2677a: add initial design 2023-10-02 15:10:04 +08:00
axi_ltc2387 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_pulse_gen Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_pwm_gen Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_rd_wr_combiner Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_spdif_rx Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_spdif_tx Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_sysid Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_tdd Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
cn0363 Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
common up_dac_channel: Cosmetics - fix indentation 2023-10-02 11:14:57 +03:00
cordic_demod Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
data_offload data_offload: Fix error regarding invalid value for param MEM_TYPE 2023-09-29 14:57:03 +03:00
intel Add copyright & license for all files needing ADI JESD specific license 2023-09-07 10:45:49 +03:00
interfaces Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
jesd204 library/common: Added DAC custom read/write interface in up_dac_common. 2023-10-02 11:07:08 +03:00
scripts adi_xilinx_device_info: Update speed_grade_list 2023-07-25 19:49:33 +03:00
spi_engine SPI Engine: Fixed delay behaviour on Chip-Select and Sleep instructions (#1200) 2023-10-30 09:52:04 -03:00
sysid_rom Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_adcfifo Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_axis_fifo Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_axis_fifo_asym Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_axis_resize Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_axis_upscale Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_bsplit Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_cdc Fix error regarding hierarchy that Vivado misses 2023-08-01 18:12:40 +03:00
util_cic Fix error regarding hierarchy that Vivado misses 2023-08-01 18:12:40 +03:00
util_dacfifo Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_dec256sinc24b Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_delay Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_do_ram Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_extract Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_fir_dec Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_fir_int Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_gmii_to_rgmii Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_hbm Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_i2c_mixer Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_mfifo Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_mii_to_rmii Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_pack Fix error regarding hierarchy that Vivado misses 2023-08-01 18:12:40 +03:00
util_pad Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_pulse_gen Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_rfifo Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_sigma_delta_spi Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_tdd_sync Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_var_fifo Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
util_wfifo Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
xilinx xilinx/ad_data_in.v: Add SDR support 2023-09-07 10:43:29 +03:00
Makefile axi_ad4858: Initial commit 2023-10-05 10:19:03 +03:00