pluto_hdl_adi/library/xilinx/axi_adcfifo
Lars-Peter Clausen 55daa786fa axi_adcfifo: Add missing constraints
Add missing timing exceptions on paths between the DMA and DDR clock
domains. All these paths are properly synchronized using CDC in the HDL,
but are missing timing exceptions in the XDC file. This can lead to timing
errors when building a design using the axi_adc_fifo.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-13 19:52:48 +02:00
..
Makefile updated makefiles 2016-12-09 23:06:41 +02:00
axi_adcfifo.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
axi_adcfifo_adc.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
axi_adcfifo_constr.xdc axi_adcfifo: Add missing constraints 2017-09-13 19:52:48 +02:00
axi_adcfifo_dma.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
axi_adcfifo_ip.tcl library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
axi_adcfifo_rd.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
axi_adcfifo_wr.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00