f3daf0dacb
Reset the fifo_rd_data if the DMA does not have an active transfer. Becasue all the DAC device cores are transfering the data from the FIFO interface to the data interface without any validation signal, DMA needs to put the data bus into a known state, to prevent the device core to send the last known data again and again. |
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README.md |
README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects
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