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pluto_hdl_adi/library/xilinx/axi_dacfifo
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Istvan Csomortani f326c03ff3 axi_dacfifo: Define constraint for bypass 
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
 		2017-02-24 12:35:42 +02:00
..
Makefile axi_dacfifo: Redesign the bypass functionality 2017-02-23 17:32:31 +02:00
axi_dacfifo.v axi_dacfifo: Define constraint for bypass 2017-02-24 12:35:42 +02:00
axi_dacfifo_bypass.v axi_dacfifo: Redesign the bypass functionality 2017-02-23 17:32:31 +02:00
axi_dacfifo_constr.xdc axi_dacfifo: Redesign the bypass functionality 2017-02-23 17:32:31 +02:00
axi_dacfifo_dac.v axi_dacfifo: Register the dac_valid signals 2017-02-24 12:34:58 +02:00
axi_dacfifo_ip.tcl axi_dacfifo: Redesign the bypass functionality 2017-02-23 17:32:31 +02:00
axi_dacfifo_rd.v axi_dacfifo: Move IP to library/xilinx 2016-09-15 11:38:16 +03:00
axi_dacfifo_wr.v axi_dacfifo: Data from DMA is validated with dma_ready too 2017-02-24 12:32:25 +02:00