pluto_hdl_adi/library/xilinx
Istvan Csomortani f326c03ff3 axi_dacfifo: Define constraint for bypass
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-02-24 12:35:42 +02:00
..
axi_adcfifo axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter 2017-02-16 19:54:41 +02:00
axi_adxcvr Makefiles: fixed axi_adxcvr/util_adxcvr Makefiles to include interfaces dependancy 2017-02-23 16:16:34 +02:00
axi_dacfifo axi_dacfifo: Define constraint for bypass 2017-02-24 12:35:42 +02:00
axi_xcvrlb updated makefiles 2016-12-09 23:06:41 +02:00
common ad_lvds_in- ultrascale/ultrascale+ sim device mess 2017-01-21 20:54:21 -05:00
util_adxcvr Makefiles: fixed axi_adxcvr/util_adxcvr Makefiles to include interfaces dependancy 2017-02-23 16:16:34 +02:00