Laszlo Nagy b7d48b8c74 common/vcu118: Balance clocks ... Minimize skew on synchronous CDC timing paths between clocks originating from the same MMCM source. (sys_mem_clk and sys_cpu_clk) This is required mostly by the smart interconnect. The CLOCK_DELAY_GROUP property must be applied directly to the output net of BUFGs.		2019-09-16 10:00:14 +03:00
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vcu118_system_bd.tcl	system_id: deployed ip	2019-08-06 16:53:11 +03:00
vcu118_system_constr.xdc	common/vcu118: Balance clocks	2019-09-16 10:00:14 +03:00