Istvan Csomortani 80333573c7 ad_fmclidar1_ebz/zcu102: Fix SYSREF input delay constraint ... Add one clock cycle input delay for the SYSREF input, to compensate the high propegation delay of device_clk_BUFG.		2019-10-17 09:59:23 +03:00
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Makefile	ad_fmclidar1_ebz: Add support for ZCU102	2019-10-17 09:59:23 +03:00
system_bd.tcl	ad_fmclidar1_ebz: Move afe_iic definition to system_bd.tcl	2019-10-17 09:59:23 +03:00
system_constr.xdc	ad_fmclidar1_ebz/zcu102: Fix SYSREF input delay constraint	2019-10-17 09:59:23 +03:00
system_project.tcl	ad_fmclidar1_ebz: Add support for ZCU102	2019-10-17 09:59:23 +03:00
system_top.v	ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location	2019-10-17 09:59:23 +03:00