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pluto_hdl_adi/library/axi_ad9361
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AndreiGrozav 7dcaaea04e library: Update scripts/adi_ad_ip.tcl and IPs 
Fix library makefiles dep list using generic vendor info reg

Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure.
This change will simplify the process of generating makefiles for each library.
Removing the bd.tcl script from the adi_ip_files list will remove it from the
make dependency list.
 		2019-04-09 16:07:14 +03:00
..
altera Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
xilinx Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
Makefile axi_ad9361: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
axi_ad9361.v Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9361_constr.sdc library/axi_ad9361: tdd false paths 2016-05-04 13:42:12 -04:00
axi_ad9361_constr.xdc axi_ad9361: Update constraint file 2017-08-04 16:20:33 +01:00
axi_ad9361_delay.tcl move/rename - delay script belongs to ad9361 2017-03-10 12:44:32 -05:00
axi_ad9361_hw.tcl Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9361_ip.tcl library: Update scripts/adi_ad_ip.tcl and IPs 2019-04-09 16:07:14 +03:00
axi_ad9361_rx.v Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9361_rx_channel.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9361_rx_pnmon.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9361_tdd.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9361_tdd_if.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9361_tx.v Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9361_tx_channel.v axi_ad9361: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00