Laszlo Nagy 5edc798b6b axi_jesd204_common/jesd204_up_common: Add event stats ... Add statistics for : - number of link enable events - number of interrupt events (regardless of mask) 0x0B0 0x2C0 Stats Control Register [0] - Write 1 to clear stat registers 0x0B1 0x2C4 Link Enable Stat Register [15:0] Number of times the link was enabled from power-on or from last stat clear 0x0B4 0x2D0 IRQ Stat Register 0 [31:16] IRQ 1 counter [15:0] IRQ 0 counter 0x0B5 0x2D4 IRQ Stat Register 1 [31:16] IRQ 3 counter [15:0] IRQ 2 counter 0x0B6 0x2D8 IRQ Stat Register 2 [31:16] IRQ 5 counter [15:0] IRQ 4 counter 0x0B7 0x2DC IRQ Stat Register 3 [31:16] IRQ 7 counter [15:0] IRQ 6 counter		2020-09-29 17:27:42 +03:00
..
Makefile	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
axi_jesd204_tx.v	axi_jesd204_common/jesd204_up_common: Add event stats	2020-09-29 17:27:42 +03:00
axi_jesd204_tx_constr.sdc	jesd204: Fix constraints for axi_jesd_tx	2018-05-10 18:17:32 +03:00
axi_jesd204_tx_constr.xdc	axi_jesd204_tx: Fix multi-link constraints	2018-08-28 15:38:49 +02:00
axi_jesd204_tx_hw.tcl	library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl	2019-06-29 06:53:51 +03:00
axi_jesd204_tx_ip.tcl	axi_jesd204_tx: Add 64b mode for control interface	2020-02-10 09:47:07 +02:00
axi_jesd204_tx_ooc.ttcl	jesd204:axi_jesd204_tx: set OOC default clock constraints	2019-04-22 10:27:16 +03:00
jesd204_up_tx.v	sync_bits: Change I/O names of wires "in" and "out" for VHDL users	2019-04-23 18:03:23 +03:00