Istvan Csomortani 11f41d1dff zynq_plddr3: Fix PLDDR3's Reset Generator ... Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset. Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to set this two property of the reset generator.		2014-12-04 15:42:28 +02:00
..
a5gt	a5gt: ethernet i/o changed to lvds	2014-09-04 11:19:24 -04:00
a5gte	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
a5soc	a5soc: fmcjesdadc1+hdmi version	2014-08-14 09:05:38 -04:00
ac701	common: Updated common constratins for ac701, kc705, vc707, zc702	2014-11-11 12:35:44 +02:00
c5soc	projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI.	2014-08-27 21:46:23 +03:00
kc705	kc705_base: Define sys_addr_mem_seg for dmafifo	2014-11-26 15:38:41 +02:00
kcu105	kcu105: ddr - 800M	2014-11-06 16:50:37 -05:00
mitx045	mitx045_common: Definition file patch	2014-11-21 19:14:37 +02:00
ml605	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
vc707	common: Updated common constratins for ac701, kc705, vc707, zc702	2014-11-11 12:35:44 +02:00
xilinx	dmafifo: parameterized address width	2014-11-20 09:28:02 -05:00
zc702	common: Updated common constratins for ac701, kc705, vc707, zc702	2014-11-11 12:35:44 +02:00
zc706	zynq_plddr3: Fix PLDDR3's Reset Generator	2014-12-04 15:42:28 +02:00
zed	zed_base: Interrupt update	2014-10-30 19:00:05 +02:00