75 lines
2.6 KiB
Verilog
75 lines
2.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_delay #(
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parameter DATA_WIDTH = 1,
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// the minimum valid value for DELAY_CYCLES is 1
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parameter DELAY_CYCLES = 1) (
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input clk,
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input reset,
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input din,
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output [DATA_WIDTH-1:0] dout);
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reg [DATA_WIDTH-1:0] dbuf[0:(DELAY_CYCLES-1)];
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always @(posedge clk) begin
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if (reset) begin
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dbuf[0] <= 0;
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end else begin
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dbuf[0] <= din;
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end
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end
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generate
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genvar i;
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for (i = 1; i < DELAY_CYCLES; i=i+1) begin:register_pipe
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always @(posedge clk) begin
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if (reset) begin
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dbuf[i] <= 0;
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end else begin
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dbuf[i] <= dbuf[i-1];
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end
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end
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end
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endgenerate
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assign dout = dbuf[(DELAY_CYCLES-1)];
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endmodule
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