127 lines
4.5 KiB
Verilog
127 lines
4.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_xfer_cntrl #(
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parameter DATA_WIDTH = 8) (
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// up interface
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input up_rstn,
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input up_clk,
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input [(DATA_WIDTH-1):0] up_data_cntrl,
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output up_xfer_done,
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// device interface
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input d_rst,
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input d_clk,
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output [(DATA_WIDTH-1):0] d_data_cntrl);
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// internal registers
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reg up_xfer_state_m1 = 'd0;
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reg up_xfer_state_m2 = 'd0;
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reg up_xfer_state = 'd0;
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reg [ 5:0] up_xfer_count = 'd0;
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reg up_xfer_done_int = 'd0;
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reg up_xfer_toggle = 'd0;
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reg [(DATA_WIDTH-1):0] up_xfer_data = 'd0;
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reg d_xfer_toggle_m1 = 'd0;
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reg d_xfer_toggle_m2 = 'd0;
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reg d_xfer_toggle_m3 = 'd0;
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reg d_xfer_toggle = 'd0;
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reg [(DATA_WIDTH-1):0] d_data_cntrl_int = 'd0;
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// internal signals
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wire up_xfer_enable_s;
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wire d_xfer_toggle_s;
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// device control transfer
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assign up_xfer_done = up_xfer_done_int;
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assign up_xfer_enable_s = up_xfer_state ^ up_xfer_toggle;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_xfer_state_m1 <= 'd0;
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up_xfer_state_m2 <= 'd0;
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up_xfer_state <= 'd0;
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up_xfer_count <= 'd0;
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up_xfer_done_int <= 'd0;
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up_xfer_toggle <= 'd0;
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up_xfer_data <= 'd0;
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end else begin
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up_xfer_state_m1 <= d_xfer_toggle;
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up_xfer_state_m2 <= up_xfer_state_m1;
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up_xfer_state <= up_xfer_state_m2;
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up_xfer_count <= up_xfer_count + 1'd1;
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up_xfer_done_int <= (up_xfer_count == 6'd1) ? ~up_xfer_enable_s : 1'b0;
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if ((up_xfer_count == 6'd1) && (up_xfer_enable_s == 1'b0)) begin
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up_xfer_toggle <= ~up_xfer_toggle;
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up_xfer_data <= up_data_cntrl;
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end
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end
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end
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assign d_data_cntrl = d_data_cntrl_int;
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assign d_xfer_toggle_s = d_xfer_toggle_m3 ^ d_xfer_toggle_m2;
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always @(posedge d_clk or posedge d_rst) begin
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if (d_rst == 1'b1) begin
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d_xfer_toggle_m1 <= 'd0;
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d_xfer_toggle_m2 <= 'd0;
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d_xfer_toggle_m3 <= 'd0;
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d_xfer_toggle <= 'd0;
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d_data_cntrl_int <= 'd0;
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end else begin
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d_xfer_toggle_m1 <= up_xfer_toggle;
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d_xfer_toggle_m2 <= d_xfer_toggle_m1;
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d_xfer_toggle_m3 <= d_xfer_toggle_m2;
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d_xfer_toggle <= d_xfer_toggle_m3;
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if (d_xfer_toggle_s == 1'b1) begin
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d_data_cntrl_int <= up_xfer_data;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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