pluto_hdl_adi/projects/common/zc706
Istvan Csomortani 34ffa15b12 zynq_plddr3: Fix PLDDR3's Reset Generator
Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
2014-12-04 15:39:17 +02:00
..
zc706_system_bd.tcl ad9625_fmc/zc706: ps7 interrupt updates 2014-10-29 12:13:44 -04:00
zc706_system_constr.xdc zc706: remove top level constraints 2014-10-15 14:51:02 -04:00
zc706_system_mig.prj dmafifo: axi stream interface 2014-10-15 14:50:57 -04:00
zc706_system_mig_constr.xdc dmac: create fifo interface to avoid being treated as axi control stream 2014-05-27 10:25:14 -04:00
zc706_system_plddr3.tcl zynq_plddr3: Fix PLDDR3's Reset Generator 2014-12-04 15:39:17 +02:00