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pluto_hdl_adi/library/jesd204/tb
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Lars-Peter Clausen 4df841addc jesd204: Add soft logic PCS 
Add soft logic PCS that performs 8b10b encoding for TX and character
pattern alignment and 8b10b decoding for RX.

The modules are intended to be used in combination with a transceiver that
does not have these features implemented in hard logic PCS.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-08-21 11:09:42 +02:00
..
.gitignore Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
axi_jesd204_rx_regmap_tb jesd204: axi_jesd204_rx_regmap_tb: Add missing dependency 2017-08-13 10:28:11 +02:00
axi_jesd204_rx_regmap_tb.v jesd204: axi_jesd204_{rx,tx}: Add external link domain reset 2017-08-18 18:25:12 +02:00
axi_jesd204_tx_regmap_tb Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
axi_jesd204_tx_regmap_tb.v jesd204: axi_jesd204_{rx,tx}: Add external link domain reset 2017-08-18 18:25:12 +02:00
loopback_tb jesd204_tx: Use the CDC sync_bits helper to synchronize the SYNC~ signal 2017-08-07 17:44:23 +02:00
loopback_tb.v jesd204: rx: Use standalone counter for lane latency monitor 2017-06-20 17:39:41 +02:00
run_tb.sh Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_cgs_tb Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_cgs_tb.v Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_ctrl_tb Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_ctrl_tb.v Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_lane_tb Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_lane_tb.v Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_tb Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
rx_tb.v jesd204: rx_tb: Fix some incorrect signal connections 2017-08-07 17:42:17 +02:00
scrambler_tb Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
scrambler_tb.v Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
soft_pcs_8b10b_sequence_tb jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
soft_pcs_8b10b_sequence_tb.v jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
soft_pcs_8b10b_table_tb jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
soft_pcs_8b10b_table_tb.v jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
soft_pcs_loopback_tb jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
soft_pcs_loopback_tb.v jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
soft_pcs_pattern_align_tb jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
soft_pcs_pattern_align_tb.v jesd204: Add soft logic PCS 2017-08-21 11:09:42 +02:00
tb_base.v Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
tx_ctrl_phase_tb jesd204_tx: Use the CDC sync_bits helper to synchronize the SYNC~ signal 2017-08-07 17:44:23 +02:00
tx_ctrl_phase_tb.v jesd204: tb: Fix signal width mismatch warnings 2017-06-20 17:39:41 +02:00
tx_tb jesd204_tx: Use the CDC sync_bits helper to synchronize the SYNC~ signal 2017-08-07 17:44:23 +02:00
tx_tb.v jesd204: Slightly rework sysref handling 2017-06-20 17:39:41 +02:00