Laszlo Nagy e433d3f808 ad9081_fmca_ebz: expose PLL selection as a parameter ... On the Xilinx PHY the available PLL options depends on the lane rate. Encoding is: 0 - CPLL 1 - QPLL0 2 - QPLL1 Since the selection of line rate is available from the project also the PLL selection must be exposed.		2020-04-23 17:21:05 +03:00
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common	ad9081_fmca_ebz: expose PLL selection as a parameter	2020-04-23 17:21:05 +03:00
vcu118	ad9081_fmca_ebz: expose PLL selection as a parameter	2020-04-23 17:21:05 +03:00
zcu102	ad9081_fmca_ebz:zcu102: initial version	2020-03-10 18:19:03 +02:00
Makefile	ad9081_fmca_ebz: common block design	2020-03-10 18:19:03 +02:00