Laszlo Nagy ddd8a14790 ad9081_fmca_ebz: Remove system reset from Xilinx PHY ... Reset in device clock domain caused timing failures. Since link reconfiguration is not supported the reset is not required.		2021-02-05 15:24:15 +02:00
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a10soc	ad9081_fmca_ebz/a10soc: Np 12 support	2021-02-05 15:24:15 +02:00
common	ad9081_fmca_ebz: Remove system reset from Xilinx PHY	2021-02-05 15:24:15 +02:00
vcu118	ad9081_fmca_ebz: Np 12 support	2021-02-05 15:24:15 +02:00
zc706	ad9081_fmca_ebz: Np 12 support	2021-02-05 15:24:15 +02:00
zcu102	ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency	2021-02-05 15:24:15 +02:00
Makefile	ad9081_fmca_ebz: common block design	2020-03-10 18:19:03 +02:00