117 lines
4.3 KiB
Tcl
117 lines
4.3 KiB
Tcl
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package require qsys 14.0
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package require quartus::device
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_intel.tcl
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ad_ip_create axi_ad9122 {AXI AD9122 Interface}
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set_module_property VALIDATION_CALLBACK info_param_validate
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ad_ip_files axi_ad9122 [list \
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$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
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$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
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$ad_hdl_dir/library/common/ad_dds_sine.v \
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$ad_hdl_dir/library/common/ad_dds_2.v \
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$ad_hdl_dir/library/common/ad_dds_1.v \
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$ad_hdl_dir/library/common/ad_dds.v \
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$ad_hdl_dir/library/intel/common/ad_mul.v \
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$ad_hdl_dir/library/common/ad_rst.v \
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$ad_hdl_dir/library/common/up_axi.v \
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$ad_hdl_dir/library/common/up_xfer_cntrl.v \
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$ad_hdl_dir/library/common/up_xfer_status.v \
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$ad_hdl_dir/library/common/up_clock_mon.v \
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$ad_hdl_dir/library/common/up_dac_common.v \
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$ad_hdl_dir/library/common/up_dac_channel.v \
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axi_ad9122_channel.v \
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axi_ad9122_core.v \
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axi_ad9122_if.v \
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axi_ad9122.v \
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$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
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$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
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$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
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$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
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axi_ad9122_constr.sdc] \
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axi_ad9122_fileset
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# parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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add_parameter FPGA_TECHNOLOGY INTEGER 0
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set_parameter_property FPGA_TECHNOLOGY DEFAULT_VALUE 0
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set_parameter_property FPGA_TECHNOLOGY DISPLAY_NAME FPGA_TECHNOLOGY
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set_parameter_property FPGA_TECHNOLOGY TYPE INTEGER
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set_parameter_property FPGA_TECHNOLOGY UNITS None
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set_parameter_property FPGA_TECHNOLOGY HDL_PARAMETER true
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adi_add_auto_fpga_spec_params
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# axi4 slave
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
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# dac device interface
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add_interface device_if conduit end
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set_interface_property device_if associatedClock none
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set_interface_property device_if associatedReset none
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add_interface_port device_if dac_clk_in_p dac_clk_in_p Input 1
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add_interface_port device_if dac_clk_in_n dac_clk_in_n Input 1
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add_interface_port device_if dac_clk_out_p dac_clk_out_p Output 1
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add_interface_port device_if dac_clk_out_n dac_clk_out_n Output 1
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add_interface_port device_if dac_frame_out_p dac_frame_out_p Output 1
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add_interface_port device_if dac_frame_out_n dac_frame_out_n Output 1
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add_interface_port device_if dac_data_out_p dac_data_out_p Output 16
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add_interface_port device_if dac_data_out_n dac_data_out_n Output 16
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add_interface_port device_if dac_sync_out dac_sync_out Output 1
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add_interface_port device_if dac_sync_in dac_sync_in Input 1
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# dma interface
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ad_interface clock dac_div_clk Output 1
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add_interface dac_ch_0 conduit end
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add_interface_port dac_ch_0 dac_valid_0 valid Output 1
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add_interface_port dac_ch_0 dac_enable_0 enable Output 1
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add_interface_port dac_ch_0 dac_ddata_0 data Input 64
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set_interface_property dac_ch_0 associatedClock if_dac_div_clk
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set_interface_property dac_ch_0 associatedReset none
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add_interface dac_ch_1 conduit end
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add_interface_port dac_ch_1 dac_valid_1 valid Output 1
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add_interface_port dac_ch_1 dac_enable_1 enable Output 1
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add_interface_port dac_ch_1 dac_ddata_1 data Input 64
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set_interface_property dac_ch_1 associatedClock if_dac_div_clk
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set_interface_property dac_ch_1 associatedReset none
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ad_interface signal dac_dunf input 1 unf
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# SERDES instances and configurations
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add_hdl_instance ad_serdes_clk_core_tx intel_serdes
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set_instance_parameter_value ad_serdes_clk_core_tx {MODE} {CLK}
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set_instance_parameter_value ad_serdes_clk_core_tx {DDR_OR_SDR_N} {1}
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set_instance_parameter_value ad_serdes_clk_core_tx {SERDES_FACTOR} {8}
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set_instance_parameter_value ad_serdes_clk_core_tx {CLKIN_FREQUENCY} {500.0}
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add_hdl_instance ad_serdes_out_core intel_serdes
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set_instance_parameter_value ad_serdes_out_core {MODE} {OUT}
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set_instance_parameter_value ad_serdes_out_core {DDR_OR_SDR_N} {1}
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set_instance_parameter_value ad_serdes_out_core {SERDES_FACTOR} {8}
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set_instance_parameter_value ad_serdes_out_core {CLKIN_FREQUENCY} {500.0}
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proc axi_ad9122_fileset { entityName } {
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ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
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ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core_tx
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}
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