300 lines
9.8 KiB
Verilog
300 lines
9.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9671 #(
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parameter ID = 0,
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parameter QUAD_OR_DUAL_N = 1) (
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk,
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input [ 3:0] rx_sof,
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input rx_valid,
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input [(64*QUAD_OR_DUAL_N)+63:0] rx_data,
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output rx_ready,
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// dma interface
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output adc_clk,
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output [ 7:0] adc_valid,
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output [ 7:0] adc_enable,
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output [127:0] adc_data,
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input adc_dovf,
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input adc_dunf,
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input adc_sync_in,
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output adc_sync_out,
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input [ 3:0] adc_raddr_in,
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output [ 3:0] adc_raddr_out,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [ 31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [ 31:0] s_axi_rdata,
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input s_axi_rready);
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// internal registers
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reg up_status_pn_err = 'd0;
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reg up_status_pn_oos = 'd0;
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reg up_status_or = 'd0;
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reg [ 31:0] up_rdata = 'd0;
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reg up_rack = 'd0;
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reg up_wack = 'd0;
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// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire adc_status_s;
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wire adc_sync_status_s;
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wire adc_valid_s;
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wire [ 15:0] adc_data_s[7:0];
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wire [ 7:0] adc_or_s;
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wire [ 7:0] up_adc_pn_err_s;
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wire [ 7:0] up_adc_pn_oos_s;
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wire [ 7:0] up_adc_or_s;
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wire up_wreq_s;
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wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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wire up_rreq_s;
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wire [ 13:0] up_raddr_s;
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wire [ 31:0] up_rdata_s[8:0];
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wire up_rack_s[8:0];
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wire up_wack_s[8:0];
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wire [ 31:0] adc_start_code;
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wire adc_sync;
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// signal name changes
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assign rx_ready = 1'b1;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_status_pn_err <= 'd0;
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up_status_pn_oos <= 'd0;
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up_status_or <= 'd0;
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up_rdata <= 'd0;
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up_rack <= 'd0;
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up_wack <= 'd0;
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end else begin
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up_status_pn_err <= | up_adc_pn_err_s;
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up_status_pn_oos <= | up_adc_pn_oos_s;
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up_status_or <= | up_adc_or_s;
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] |
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up_rdata_s[4] | up_rdata_s[5] | up_rdata_s[6] | up_rdata_s[7] | up_rdata_s[8];
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up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] |
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up_rack_s[4] | up_rack_s[5] | up_rack_s[6] | up_rack_s[7] | up_rack_s[8];
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up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] |
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up_wack_s[4] | up_wack_s[5] | up_wack_s[6] | up_wack_s[7] | up_wack_s[8];
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end
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end
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// main (device interface)
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axi_ad9671_if #(
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.QUAD_OR_DUAL_N (QUAD_OR_DUAL_N),
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.ID (ID)
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i_if (
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.rx_clk (rx_clk),
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.rx_data (rx_data),
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.rx_sof (rx_sof),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid_s),
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.adc_data_a (adc_data_s[0]),
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.adc_or_a (adc_or_s[0]),
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.adc_data_b (adc_data_s[1]),
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.adc_or_b (adc_or_s[1]),
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.adc_data_c (adc_data_s[2]),
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.adc_or_c (adc_or_s[2]),
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.adc_data_d (adc_data_s[3]),
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.adc_or_d (adc_or_s[3]),
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.adc_data_e (adc_data_s[4]),
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.adc_or_e (adc_or_s[4]),
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.adc_data_f (adc_data_s[5]),
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.adc_or_f (adc_or_s[5]),
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.adc_data_g (adc_data_s[6]),
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.adc_or_g (adc_or_s[6]),
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.adc_data_h (adc_data_s[7]),
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.adc_or_h (adc_or_s[7]),
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.adc_start_code (adc_start_code),
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.adc_sync (adc_sync),
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.adc_sync_in (adc_sync_in),
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.adc_sync_out (adc_sync_out),
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.adc_sync_status (adc_sync_status_s),
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.adc_status (adc_status_s),
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.adc_raddr_in (adc_raddr_in),
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.adc_raddr_out (adc_raddr_out));
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// channels
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genvar n;
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generate
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for (n = 0; n < 8; n = n + 1) begin: g_channel
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axi_ad9671_channel #(.CHANNEL_ID(n)) i_channel (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid_s),
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.adc_data (adc_data_s[n]),
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.adc_or (adc_or_s[n]),
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.adc_dfmt_valid (adc_valid[n]),
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.adc_dfmt_data (adc_data[(n*16)+15:(n*16)]),
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.adc_enable (adc_enable[n]),
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.up_adc_pn_err (up_adc_pn_err_s[n]),
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.up_adc_pn_oos (up_adc_pn_oos_s[n]),
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.up_adc_or (up_adc_or_s[n]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[n]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[n]),
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.up_rack (up_rack_s[n]));
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end
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endgenerate
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// common processor control
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up_adc_common #(.ID (ID)) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status (adc_status_s),
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.adc_sync_status (adc_sync_status_s),
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.adc_status_ovf (adc_dovf),
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.adc_status_unf (adc_dunf),
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.adc_clk_ratio (32'd1),
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.adc_start_code (adc_start_code),
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.adc_sref_sync (),
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.adc_sync (adc_sync),
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.up_adc_ce (),
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.up_status_pn_err (up_status_pn_err),
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.up_status_pn_oos (up_status_pn_oos),
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.up_status_or (up_status_or),
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.up_drp_sel (),
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.up_drp_wr (),
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.up_drp_addr (),
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.up_drp_wdata (),
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.up_drp_rdata (32'd0),
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.up_drp_ready (1'd0),
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.up_drp_locked (1'd1),
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.up_usr_chanmax_out (),
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.up_usr_chanmax_in (8'd7),
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.up_adc_gpio_in (32'd0),
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.up_adc_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[8]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[8]),
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.up_rack (up_rack_s[8]));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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