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pluto_hdl_adi/library
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AndreiGrozav 66823682b6 Add FPGA info parameters flow 
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
 		2019-03-30 11:26:11 +02:00
..
altera Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad5766 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad6676 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad7616 Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_ad9122 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9144 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9152 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9162 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9250 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9265 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9361 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9371 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9434 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9467 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9625 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9671 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9680 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9684 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9739a Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9963 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_adc_decimate Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_adc_trigger axi_adc_trigger: Cosmetic update 2019-02-18 13:39:24 +02:00
axi_adrv9009 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_clkgen Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_dac_interpolate Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_dmac Makefile: update makefiles 2018-12-21 17:32:48 +02:00
axi_fmcadc5_sync Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_generic_adc Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_gpreg axi_gpreg: Use the common ad_rst constraints 2018-08-06 21:24:41 +03:00
axi_hdmi_rx ad_csc: Generalize for CrYCB 2 RGB conversion 2019-02-12 10:43:46 +02:00
axi_hdmi_tx Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_i2s_adi axi_i2s_adi: fixed xdc 2019-03-18 13:58:28 +00:00
axi_intr_monitor Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_logic_analyzer ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
axi_mc_controller Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_mc_current_monitor all: Drive undriven input signals, complete interface 2018-08-10 17:00:11 +03:00
axi_mc_speed all: Drive undriven input signals, complete interface 2018-08-10 17:00:11 +03:00
axi_pulse_gen axi_pulse_gen: Initial commit 2019-03-20 08:21:22 +00:00
axi_rd_wr_combiner axi_rd_wr_combiner: Add rlast to the AXI MM interface 2019-02-21 17:09:53 +02:00
axi_spdif_rx axi_spdif_rx: clear warning 2018-08-10 17:00:11 +03:00
axi_spdif_tx adi_ip: Use 'associate_bus_interface' command to setup the clock and reset for s_axi 2018-08-06 10:14:48 +03:00
axi_usb_fx3 Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
cn0363 Add missing timescale annotations 2018-10-17 10:32:47 +03:00
common Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
cordic_demod Add missing timescale annotations 2018-10-17 10:32:47 +03:00
interfaces axi|util_adxcvr: Expose TX configurable driver ports 2018-10-04 14:37:02 +03:00
jesd204 Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
scripts library/scripts: Add auto dev spec parameters 2019-03-30 11:26:11 +02:00
spi_engine Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_adcfifo Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
util_axis_fifo util_axis_fifo: Fix the FIFO level generation in ASYNC mode 2019-01-29 11:38:28 +02:00
util_axis_resize Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_axis_upscale Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_bsplit library: Remove empty constraint files 2018-04-11 15:09:54 +03:00
util_cdc Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_cic Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_clkdiv Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_dacfifo Makefile: update makefiles 2018-12-21 17:32:48 +02:00
util_delay Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_extract Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_fir_dec Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_fir_int Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_gmii_to_rgmii Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_i2c_mixer Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_mfifo Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_pack Add util_cpack2 core 2018-11-28 11:33:11 +02:00
util_pulse_gen Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_rfifo Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_sigma_delta_spi Add missing timescale annotations 2018-10-17 10:32:47 +03:00
util_tdd_sync util_tdd_sync: Fix util_pulse_gen instantiation 2019-03-21 07:28:18 +00:00
util_var_fifo Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_wfifo Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
xilinx Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
Makefile axi_pulse_gen: Initial commit 2019-03-20 08:21:22 +00:00