pluto_hdl_adi/library/xilinx
Istvan Csomortani 758c617c77 common/up_* : Make up_rstn synchronous to up_clk
The up_rstn is driven by s_axi_resetn, which is generated by a
Processor System Reset module. (connected to port peripheral_aresetn)
Therefor using this reset signal as an asynchronous reset is redundant,
and a bad design practice at the same time. Asynchronous reset should be
used if it's inevitable.
2018-04-11 15:09:54 +03:00
..
axi_adcfifo axi_adcfifo: Add missing constraints 2017-09-13 19:52:48 +02:00
axi_adxcvr Make: Use $(MAKE) for recursive make commands 2018-03-07 07:40:19 +00:00
axi_dacfifo Make: Update makefiles 2017-11-20 14:27:39 +02:00
axi_xcvrlb library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size 2017-08-01 15:21:25 +02:00
common common/up_* : Make up_rstn synchronous to up_clk 2018-04-11 15:09:54 +03:00
util_adxcvr Make: Use $(MAKE) for recursive make commands 2018-03-07 07:40:19 +00:00