Adrian Costina c32b4b02f3 sync_bits: Change I/O names of wires "in" and "out" for VHDL users		2019-04-23 18:03:23 +03:00
..
Makefile	jesd204:axi_jesd204_rx: set OOC default clock constraints	2019-04-22 10:27:16 +03:00
axi_jesd204_rx.v	Add missing timescale annotations	2018-10-17 10:32:47 +03:00
axi_jesd204_rx_constr.sdc	jesd204: Add RX error statistics (#98)	2018-05-07 15:33:00 +03:00
axi_jesd204_rx_constr.xdc	jesd204: Add constraints for the rx statistics clock crossing	2018-05-10 16:32:50 +03:00
axi_jesd204_rx_hw.tcl	jesd204: Add RX error statistics (#98)	2018-05-07 15:33:00 +03:00
axi_jesd204_rx_ip.tcl	jesd204:axi_jesd204_rx: set OOC default clock constraints	2019-04-22 10:27:16 +03:00
axi_jesd204_rx_ooc.ttcl	jesd204:axi_jesd204_rx: set OOC default clock constraints	2019-04-22 10:27:16 +03:00
jesd204_up_ilas_mem.v	sync_bits: Change I/O names of wires "in" and "out" for VHDL users	2019-04-23 18:03:23 +03:00
jesd204_up_rx.v	Add missing timescale annotations	2018-10-17 10:32:47 +03:00
jesd204_up_rx_lane.v	sync_bits: Change I/O names of wires "in" and "out" for VHDL users	2019-04-23 18:03:23 +03:00