244 lines
9.3 KiB
Verilog
244 lines
9.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg_top#(
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parameter NUM_CHANNEL = 4,
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parameter ADC_EN = 1,
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parameter DAC_EN = 1) (
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input clk,
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// gpio
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input [31:0] dac_gpio_input,
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output [31:0] dac_gpio_output,
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input [31:0] adc_gpio_input,
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output [31:0] adc_gpio_output,
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// TX side
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input dma_dac_0_enable,
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output [(DBUS_WIDTH-1):0] dma_dac_0_data,
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input dma_dac_0_valid,
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input dma_dac_1_enable,
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output [(DBUS_WIDTH-1):0] dma_dac_1_data,
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input dma_dac_1_valid,
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input dma_dac_2_enable,
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output [(DBUS_WIDTH-1):0] dma_dac_2_data,
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input dma_dac_2_valid,
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input dma_dac_3_enable,
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output [(DBUS_WIDTH-1):0] dma_dac_3_data,
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input dma_dac_3_valid,
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output core_dac_0_enable,
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input [(DBUS_WIDTH-1):0] core_dac_0_data,
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output core_dac_0_valid,
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output core_dac_1_enable,
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input [(DBUS_WIDTH-1):0] core_dac_1_data,
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output core_dac_1_valid,
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output core_dac_2_enable,
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input [(DBUS_WIDTH-1):0] core_dac_2_data,
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output core_dac_2_valid,
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output core_dac_3_enable,
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input [(DBUS_WIDTH-1):0] core_dac_3_data,
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output core_dac_3_valid,
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// RX side
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input dma_adc_0_enable,
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input [(DBUS_WIDTH-1):0] dma_adc_0_data,
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input dma_adc_0_valid,
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input dma_adc_1_enable,
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input [(DBUS_WIDTH-1):0] dma_adc_1_data,
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input dma_adc_1_valid,
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input dma_adc_2_enable,
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input [(DBUS_WIDTH-1):0] dma_adc_2_data,
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input dma_adc_2_valid,
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input dma_adc_3_enable,
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input [(DBUS_WIDTH-1):0] dma_adc_3_data,
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input dma_adc_3_valid,
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output core_adc_0_enable,
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output [(DBUS_WIDTH-1):0] core_adc_0_data,
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output core_adc_0_valid,
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output core_adc_1_enable,
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output [(DBUS_WIDTH-1):0] core_adc_1_data,
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output core_adc_1_valid,
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output core_adc_2_enable,
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output [(DBUS_WIDTH-1):0] core_adc_2_data,
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output core_adc_2_valid,
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output core_adc_3_enable,
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output [(DBUS_WIDTH-1):0] core_adc_3_data,
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output core_adc_3_valid);
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localparam ENABELED = 1;
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localparam DATA_WIDTH = 16;
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localparam DBUS_WIDTH = DATA_WIDTH * NUM_CHANNEL;
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wire [31:0] adc_gpio_out_s[(NUM_CHANNEL - 1):0];
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wire [(NUM_CHANNEL - 1):0] adc_gpio_out_s_inv[31:0];
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wire [31:0] dac_gpio_out_s[(NUM_CHANNEL - 1):0];
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wire [(NUM_CHANNEL - 1):0] dac_gpio_out_s_inv[31:0];
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wire [(NUM_CHANNEL - 1):0] core_adc_enable_s;
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wire [(NUM_CHANNEL - 1):0] core_adc_valid_s;
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wire [(NUM_CHANNEL - 1):0] core_adc_data_s[15:0];
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wire [(NUM_CHANNEL - 1):0] dma_adc_enable_s;
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wire [(NUM_CHANNEL - 1):0] dma_adc_valid_s;
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wire [(NUM_CHANNEL - 1):0] dma_adc_data_s[15:0];
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wire [(NUM_CHANNEL - 1):0] core_dac_enable_s;
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wire [(NUM_CHANNEL - 1):0] core_dac_valid_s;
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wire [(NUM_CHANNEL - 1):0] core_dac_data_s[15:0];
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wire [(NUM_CHANNEL - 1):0] dma_dac_enable_s;
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wire [(NUM_CHANNEL - 1):0] dma_dac_valid_s;
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wire [(NUM_CHANNEL - 1):0] dma_dac_data_s[15:0];
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genvar l_inst;
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generate
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for(l_inst = 0; l_inst < NUM_CHANNEL; l_inst = l_inst + 1) begin: tx_rx_data_path
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if(ADC_EN == ENABELED) begin
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prcfg_adc #(
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.CHANNEL_ID(l_inst)
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) i_prcfg_adc_i (
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.clk(clk),
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.control(adc_gpio_input),
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.status(adc_gpio_out_s[l_inst]),
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.src_adc_enable(core_adc_enable_s[l_inst]),
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.src_adc_valid(core_adc_valid_s[l_inst]),
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.src_adc_data(core_adc_data_s[l_inst]),
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.dst_adc_enable(dma_adc_enable_s[l_inst]),
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.dst_adc_valid(dma_adc_valid_s[l_inst]),
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.dst_adc_data(dma_adc_data_s[l_inst])
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);
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end
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if(DAC_EN == ENABELED) begin
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prcfg_dac #(
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.CHANNEL_ID(l_inst)
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) i_prcfg_dac_i (
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.clk(clk),
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.control(dac_gpio_input),
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.status(dac_gpio_out_s[l_inst]),
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.src_dac_enable(dma_dac_enable_s[l_inst]),
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.src_dac_data(dma_dac_data_s[l_inst]),
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.src_dac_valid(dma_dac_valid_s[l_inst]),
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.dst_dac_enable(core_dac_enable_s[l_inst]),
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.dst_dac_data(core_dac_data_s[l_inst]),
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.dst_dac_valid(core_dac_valid_s[l_inst])
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);
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end
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end
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endgenerate
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genvar i;
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genvar j;
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generate
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for(i = 0; i < 32; i = i + 1) begin
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for(j = 0; j < NUM_CHANNEL; j = j + 1) begin
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assign adc_gpio_out_s_inv[i][j] = adc_gpio_out_s[j][i];
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assign dac_gpio_out_s_inv[i][j] = dac_gpio_out_s[j][i];
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end
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end
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endgenerate
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// generate gpio_outputs
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generate
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for(i = 0; i < 32; i = i + 1) begin
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assign adc_gpio_output[i] = |adc_gpio_out_s_inv[i];
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assign dac_gpio_output[i] = |dac_gpio_out_s_inv[i];
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end
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endgenerate
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// port connections
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assign core_dac_0_enable = core_dac_enable_s[0];
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assign core_dac_0_valid = core_dac_valid_s[0];
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assign core_dac_data_s[0] = core_dac_0_data;
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assign core_dac_1_enable = core_dac_enable_s[1];
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assign core_dac_1_valid = core_dac_valid_s[1];
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assign core_dac_data_s[1] = core_dac_1_data;
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assign core_dac_2_enable = core_dac_enable_s[2];
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assign core_dac_2_valid = core_dac_valid_s[2];
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assign core_dac_data_s[2] = core_dac_2_data;
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assign core_dac_3_enable = core_dac_enable_s[3];
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assign core_dac_3_valid = core_dac_valid_s[3];
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assign core_dac_data_s[3] = core_dac_3_data;
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assign dma_dac_enable_s[0] = dma_dac_0_enable;
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assign dma_dac_valid_s[0] = dma_dac_0_valid;
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assign dma_dac_0_data = dma_dac_data_s[0];
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assign dma_dac_enable_s[1] = dma_dac_1_enable;
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assign dma_dac_valid_s[1] = dma_dac_1_valid;
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assign dma_dac_1_data = dma_dac_data_s[1];
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assign dma_dac_enable_s[2] = dma_dac_2_enable;
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assign dma_dac_valid_s[2] = dma_dac_2_valid;
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assign dma_dac_2_data = dma_dac_data_s[2];
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assign dma_dac_enable_s[3] = dma_dac_3_enable;
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assign dma_dac_valid_s[3] = dma_dac_3_valid;
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assign dma_dac_3_data = dma_dac_data_s[3];
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assign core_adc_0_enable = core_adc_enable_s[0];
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assign core_adc_0_valid = core_adc_valid_s[0];
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assign core_adc_0_data = core_adc_data_s[0];
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assign core_adc_1_enable = core_adc_enable_s[1];
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assign core_adc_1_valid = core_adc_valid_s[1];
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assign core_adc_1_data = core_adc_data_s[1];
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assign core_adc_2_enable = core_adc_enable_s[2];
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assign core_adc_2_valid = core_adc_valid_s[2];
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assign core_adc_2_data = core_adc_data_s[2];
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assign core_adc_3_enable = core_adc_enable_s[3];
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assign core_adc_3_valid = core_adc_valid_s[3];
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assign core_adc_3_data = core_adc_data_s[3];
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assign dma_adc_enable_s[0] = dma_adc_0_enable;
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assign dma_adc_valid_s[0] = dma_adc_0_valid;
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assign dma_adc_data_s[0] = dma_adc_0_data;
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assign dma_adc_enable_s[1] = dma_adc_1_enable;
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assign dma_adc_valid_s[1] = dma_adc_1_valid;
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assign dma_adc_data_s[1] = dma_adc_1_data;
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assign dma_adc_enable_s[2] = dma_adc_2_enable;
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assign dma_adc_valid_s[2] = dma_adc_2_valid;
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assign dma_adc_data_s[2] = dma_adc_2_data;
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assign dma_adc_enable_s[3] = dma_adc_3_enable;
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assign dma_adc_valid_s[3] = dma_adc_3_valid;
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assign dma_adc_data_s[3] = dma_adc_3_data;
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endmodule
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