03682f6193
1. Reduce max allowed skew between source synchronous clocks that can occur due PCB differences. 250ps represents a difference more than an inch. 2. In order to reduce skew between source synchronous clock and the divided clock instruct the tool to use a common clock root for them. |
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| .. | ||
| a10soc | ||
| common | ||
| zc706 | ||
| zcu102 | ||
| zed | ||
| Makefile | ||