Lars-Peter Clausen 2e173201d4 daq2: daq2_qsys.tcl: Use sys_dma_clk ... Use the sys_dma_clk clock module for clock and reset signals of the data path, rather than using the A10GX specific sys_ddr3_cntrl signals. This enables compatibility for all Altera/Intel platforms. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-07-17 17:38:20 +02:00
..
daq2_bd.tcl	Connect JESD204 interrupts	2017-07-05 14:37:50 +02:00
daq2_qsys.tcl	daq2: daq2_qsys.tcl: Use sys_dma_clk	2017-07-17 17:38:20 +02:00
daq2_spi.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00