135 lines
4.3 KiB
Verilog
135 lines
4.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module axi_repack (
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input clk,
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input resetn,
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input s_valid,
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output s_ready,
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input [C_S_DATA_WIDTH-1:0] s_data,
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output m_valid,
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input m_ready,
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output [C_M_DATA_WIDTH-1:0] m_data
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);
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parameter C_M_DATA_WIDTH = 64;
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parameter C_S_DATA_WIDTH = 64;
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generate if (C_S_DATA_WIDTH == C_M_DATA_WIDTH) begin
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assign m_valid = s_valid;
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assign s_ready = m_ready;
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assign m_data = s_data;
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end else if (C_S_DATA_WIDTH < C_M_DATA_WIDTH) begin
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localparam RATIO = C_M_DATA_WIDTH / C_S_DATA_WIDTH;
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reg [C_M_DATA_WIDTH-1:0] data;
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reg [$clog2(RATIO)-1:0] count;
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reg valid;
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always @(posedge clk)
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begin
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if (resetn == 1'b0) begin
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count <= RATIO - 1;
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valid <= 1'b0;
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end else begin
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if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1)
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valid <= 1'b1;
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else if (m_ready == 1'b1)
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valid <= 1'b0;
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if (s_ready == 1'b1 && s_valid == 1'b1)
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count <= count - 1'b1;
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end
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end
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always @(posedge clk)
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begin
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if (s_ready == 1'b1 && s_valid == 1'b1)
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data <= {s_data, data[C_M_DATA_WIDTH-1:C_S_DATA_WIDTH]};
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end
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assign s_ready = ~valid || m_ready;
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assign m_valid = valid;
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assign m_data = data;
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end else begin
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localparam RATIO = C_S_DATA_WIDTH / C_M_DATA_WIDTH;
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reg [C_S_DATA_WIDTH-1:0] data;
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reg [$clog2(RATIO)-1:0] count;
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reg valid;
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always @(posedge clk)
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begin
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if (resetn == 1'b0) begin
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count <= RATIO - 1;
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valid <= 1'b0;
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end else begin
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if (s_valid == 1'b1 && s_ready == 1'b1)
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valid <= 1'b1;
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else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1)
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valid <= 1'b0;
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if (m_ready == 1'b1 && m_valid == 1'b1)
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count <= count - 1'b1;
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end
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end
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always @(posedge clk)
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begin
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if (s_ready == 1'b1 && s_valid == 1'b1)
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data <= s_data;
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else if (m_ready == 1'b1 && m_valid == 1'b1)
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data[C_S_DATA_WIDTH-C_M_DATA_WIDTH-1:0] <= data[C_S_DATA_WIDTH-1:C_M_DATA_WIDTH];
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end
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assign s_ready = ~valid || (m_ready && count == 'h0);
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assign m_valid = valid;
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assign m_data = data[C_M_DATA_WIDTH-1:0];
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end
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endgenerate
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endmodule
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